畢業(yè)設(shè)計(jì)-基于vhdl的數(shù)字是競(jìng)賽搶答器的設(shè)計(jì)與實(shí)現(xiàn)(已修改)
2024-12-19 19:12 本頁(yè)面
【正文】 基于 VHDL的數(shù)字式競(jìng)賽搶答器的設(shè)計(jì)與實(shí)現(xiàn) 搶答、計(jì)分和報(bào)警 完成日期： 指導(dǎo)教師簽字： 答辯小組成員簽字： I 基于 VHDL的數(shù)字式競(jìng)賽搶答器的設(shè)計(jì)與實(shí)現(xiàn) —— 搶答、計(jì)分和報(bào)警 摘 要 搶答器作為一種電子產(chǎn)品，早已廣泛應(yīng)用于各種智力競(jìng)賽和知識(shí)競(jìng)賽場(chǎng)合，是競(jìng)賽問答中一種常用的必備裝置電路結(jié)構(gòu)形式多種多樣。 本設(shè)計(jì)使用 VHDL 語(yǔ)言設(shè)計(jì)一個(gè)四路數(shù)字競(jìng)賽搶答器系統(tǒng)。 VHDL 是一種全方位的硬件描述語(yǔ)言，幾 乎覆蓋了以往各種硬件描述語(yǔ)言的功能，整個(gè)自頂向下或自底向上的電路設(shè)計(jì)過程都可以用 VHDL 來完成。本文闡述了 EDA 的概念和發(fā)展、 VHDL語(yǔ)言的優(yōu)點(diǎn)和語(yǔ)法結(jié)構(gòu)并分析講解了四路數(shù)字競(jìng)賽的各模塊的功能要求、基本原理以及實(shí)現(xiàn)方法。本系統(tǒng)的設(shè)計(jì)就是采用 VHDL 硬件描述語(yǔ)言編程，基于 平臺(tái)進(jìn)行編譯和仿真來實(shí)現(xiàn)的，其采用的模塊化、逐步細(xì)化的設(shè)計(jì)方法有利于系統(tǒng)的分工合作，并且能夠及早發(fā)現(xiàn)各子模塊及系統(tǒng)中的錯(cuò)誤，提高系統(tǒng)設(shè)計(jì)的效率。搶答器的主要功能模塊是是： 對(duì)第一搶答信號(hào)的鑒別和鎖存功能； 計(jì)分功能 。 數(shù)碼顯示 ； 答題限時(shí)功能。在本設(shè)計(jì)主要講述搶答、計(jì)分和警告的功能。 關(guān)鍵詞 : 搶答器； EDA ； VHDL II Based on VHDL for Digital Competition Vies to Answer First the Design andImplementation Vies to AnswerFirst, Scoring and Call the Police Abstract Responder is a kind of electronic products, has been widely used in all kinds of intelligence petition and knowledge contests occasions, is contest answers must have a mon device circuit structure forms. The design of the use of VHDL language design a four way race responder digital is a full range of hardware description language, covering almost the past various hardware description language function, the topdown or bottomup circuit design process can use VHDL to paper expounds the concept and the development of EDA, VHDL language advantages and grammatical structure and Analysis on the four digital petition each module functional requirements, principle and implementation design of this system is the use of VHDL hardware description language, based on platform pilation and simulation to achieve, the modular, stepwise refinement design method is helpful for system of division of labour, and early identification of each module and the system error, improve the efficiency of system to answer first the main function module is: 1, the first vies to answer first the differential signal and latch function。 2, score 3, a digital display。 4, the answer time limit this design is mainly about answering, scoring and warning function. Key words: responder。 EDA。 VHDL III 目錄 1 緒論 .................................................................................................................... 1 2 總體設(shè)計(jì)方案 ..................................................................................................... 2 3 設(shè)計(jì)平臺(tái)的描述 ................................................................................................. 3 EDA 的概述 ........................................................................................................................ 3 VHDL 語(yǔ)言特點(diǎn)描述 ............................................................................................................ 4 設(shè)計(jì)平臺(tái) QUARTUSII 軟件的概述及工作原理 ......................................................... 5 4 搶答器各部分的設(shè)計(jì)描述及仿真波形 .............................................................. 7 搶答鑒別、計(jì)分和報(bào)警模塊的設(shè)計(jì) ................................................................................... 7 搶答鑒別模塊設(shè)計(jì) ...................................................................................................... 7 報(bào)警模塊設(shè)計(jì) .............................................................................................................. 8 計(jì)分模塊的設(shè)計(jì) .......................................................................................................... 9 其他模塊的設(shè)計(jì) ................................................................................
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