【正文】 I 基于 FPGA 的預(yù)測(cè)控制器 設(shè)計(jì) 摘 要 預(yù)測(cè) 控制是隨著自適應(yīng)控制的研究而發(fā)展起來的一種先進(jìn)的計(jì)算機(jī)控制算法， FPGA 具有很強(qiáng)的并行運(yùn)算能力，運(yùn)行速度快，采用 FPGA 陣列處理器實(shí)現(xiàn)預(yù)測(cè)控制系統(tǒng) ， 能大幅提高預(yù)測(cè)控制的在線優(yōu)化速度 。 本文在 Xilinx 公司的集成開發(fā)環(huán)境 中，采用硬件描述語言 HDL 編程，調(diào)用 IP 核等輸入方式，完成了預(yù)測(cè)控制改進(jìn)算法的 PPGA 設(shè)計(jì)與實(shí)現(xiàn)。論文首先介紹了廣義預(yù)測(cè)控制算法以及改進(jìn)的算法，由于算法主要涉及矩陣相關(guān)的運(yùn)算需要進(jìn)行大量的數(shù)據(jù)計(jì)算和處理，為了減少數(shù)據(jù)計(jì)算的復(fù)雜性， 從實(shí)現(xiàn)算法的控制器的硬件結(jié)構(gòu)上改進(jìn)，因此采用 FPGA陣列處理器實(shí)現(xiàn)預(yù)測(cè)控制系統(tǒng)。針對(duì)基于 FPGA硬件實(shí)現(xiàn)的特點(diǎn)介紹了求解預(yù)測(cè)控制中逆矩陣的遞推算法，設(shè)計(jì)出了預(yù)測(cè)控制的處理器陣列結(jié)構(gòu) .在設(shè)計(jì)中采用層次化，模塊化的思想，將整個(gè)算法劃分成多個(gè)功能模塊，畫出了各模塊的流程圖。包括系統(tǒng)的總體結(jié)構(gòu)設(shè)計(jì)，基本的處理器單元的設(shè)計(jì)，遞推求逆算法的處理器陣列設(shè)計(jì)，輸出預(yù)測(cè)的處理器陣列設(shè)計(jì)，控制增量的計(jì)算，參數(shù)辨識(shí)等。最后用 Modelsim 仿真軟件對(duì)各模塊進(jìn)行了仿真，給出了仿真結(jié)果。 設(shè)計(jì)中的各模塊均采用 HDL 通用硬件描述語言進(jìn) 行描述，對(duì)仿真結(jié)果進(jìn)行了分析表明 :采用 FPGA 陣列處理器實(shí)現(xiàn)預(yù)測(cè)控制系統(tǒng)，能大幅提高預(yù)測(cè)控制的在線優(yōu)化速度，減小控制器面積，擴(kuò)大預(yù)測(cè)控制的應(yīng)用領(lǐng)域 . 關(guān)鍵詞 :預(yù)測(cè)控制算法 。FPGA。處理器陣列 。矩陣求逆 。并行運(yùn)算 II Design of predictive controller based on FPGA Abstract With the development of adaptive control, predictive control is proposed. Predictive control algorithm is an advanced puter control algorithm, and based on parameter model without strict requirements to process model. FPGA system has strong parallel puting capability and higher speed in calculations. So inline optimization speed is raised. In the thesis, based on Xilinx integrated developing environment , using hardware description language as the programming language, IP core as the input, a improved predictivecontrol algorithm is designed and implemented using FPGA. General predictivecontrol algorithm and its improved format are introduced. The algorithm involves with many matrix calculation, so a lot of data puting and processing is needed. At the same time improvement from controller and hardware structure is obtained. FPGA array processor is used to implement predictivecontrol system. Due to the FPGA hardware implement, recurrent method for Matrix inversion in the predictivecontrol is briefly discussed. Predictivecontrol processor array structure is designed. In the design, adopting hierarchy and module method, the entire algorithm is divided into function modules, flows of function modules have been drawed. Such as overall system structure design, basic processor design, recurring matrix inversion processor array design, output prediction processor array design, control increment III calculation, parameter identification, and so on. Every functional module is simulated using software Modelsim. The simulation result is given. HDL description language is applied in the models of design. Analyzes the results of simulation and receives some useful conclusions. So inline optimization speed is raised and the size and cost is reduced, the application field is greatly expanded. Key words:Predictivecontrol algorithm。 FPGA。Processor arrays。 Matrix inversion。 Parallel algorithm IV 目 錄 摘 要 .................................................................................................................................. I ABSTRACT......................................................................................................................II 第 1 章 緒論 ................................................................................................................... 1 研究現(xiàn)狀概述 ..................................................................................................... 1 預(yù)測(cè)控制的發(fā)展和應(yīng)用 ..................................................................................... 3 預(yù)測(cè)控制在新應(yīng)用中面臨的問題 ..................................................................... 4 FPGA 實(shí)現(xiàn)預(yù)測(cè)控制器的優(yōu)勢(shì) .......................................................................... 5 主要內(nèi)容 ............................................................................................................. 7 第 2 章 基礎(chǔ)知識(shí) ........................................................................................................... 8 FPGA 技術(shù) .......................................................................................................... 8 FPGA 結(jié)構(gòu) ................................................................................................ 8 FPGA 特點(diǎn) .............................................................................................. 11 SOPC 技術(shù) ........................................................................................................ 11 Nios II 嵌入式軟核處理器 .............................................................................. 13 FPGA/SOPC 開發(fā)工具 .................................................................................... 14 FPGA/SOPC 開發(fā)流程 .................................................................................... 16 第 3 章 廣義預(yù)測(cè)控制算法 ........................................................................................... 19 預(yù)測(cè)控制的特點(diǎn) ............................................................................................... 19 預(yù)測(cè)模型 ................................................................................................. 19 改進(jìn)的廣義預(yù)測(cè)控制算法 ............................................................................... 21 V 預(yù)測(cè)模型 ................................................................................................. 21 最小方差預(yù)報(bào)器 ..................................................................................... 22 預(yù)測(cè)輸出 ................................................................................................. 22 參考軌跡 ................................................................................................. 23 矩陣分解 ........................................................................................................... 23 遞推求逆 ........................................................................................................... 24 第 4 章 預(yù)測(cè)控制 FPGA 實(shí)現(xiàn)的基本單元介紹 .......................................................... 26 乘法加法器： ................................................................................................... 26 移位寄 存器： .....................