【正文】 JIANGSU TEACHERS UNIVERSITY OF TECHNOLOGY 數(shù)字電路課程設(shè)計報告出租車計費器 學(xué)院名稱： 電氣信息工程學(xué)院 專 業(yè)： 通信工程 班 級： 姓 名： 學(xué) 號： 指導(dǎo)教師姓名： 2009 年 12 月摘 要隨著EDA技術(shù)的高速發(fā)展，電子系統(tǒng)的設(shè)計技術(shù)和工具發(fā)生了深刻的變化，大規(guī)模可編程邏輯器件CPLD／FPGA的出現(xiàn)，給設(shè)計人員帶來了諸多方便。利用它進(jìn)行產(chǎn)品開發(fā)，不僅成本低、周期短、可靠性高，而且具有完全的知識產(chǎn)權(quán)。利用VHDL語言設(shè)計出租車計費系統(tǒng)，使其實現(xiàn)計費以及預(yù)置和模擬汽車啟動、停止、暫停等功能，并設(shè)計動態(tài)掃描電路顯示車費數(shù)目，突出了其作為硬件描述語言的良好的可讀性、可移植性和易讀性等優(yōu)點。此程序通過下載到特定芯片后，可應(yīng)用于實際的出租車計費系統(tǒng)中。本文基于FPGA開發(fā)系統(tǒng)，在Quartus II ，完成了出租車自動計費電路的設(shè)計和硬件實現(xiàn)。首先，論文介紹了Quartus II ，采用VHDL 硬件描述語言描述出租車自動計費電路，完成對電路的功能仿真。在設(shè)計過程中，重點探討了出租車自動計費電路的設(shè)計思路和功能模塊劃分。然后，初步探討了電路邏輯綜合的原理，該軟件對出租車自動計費電路進(jìn)行了邏輯綜合。最后，使用EDA實驗開發(fā)系統(tǒng)進(jìn)行電路的下載和驗證。驗證結(jié)果表明設(shè)計的出租車自動計費電路完成了預(yù)期的功能。關(guān)鍵詞 超高速集成電路硬件描述語言，計數(shù)器，Quartus II ，高速集成電路 AbstractWith the rapid development of EDA technology, electronic system design techniques and tools have been profound changes in largescale programmable logic device CPLD / FPGA emergence of designers to bring a lot of convenience. Use it for product development, not only low cost, short cycle, high reliability and full intellectual property rights. Design using VHDL language taxi billing system, billing, as well as to achieve the preset and simulated vehicle to start, stop, pause and other functions, and circuit design of dynamic scan showed that the number of fare, highlighted as a hardware description language can be a good Reading, the portability and readability advantages. By downloading the program to a specific chip, the taxi can be applied to the actual billing system. Based on FPGA development system, in the Quartus II software platform, automatic billing taxi pleted the circuit design and hardware implementation. First of all, the paper introduced the Quartus II the basic use of software and hardware description language FPGA features, the use of VHDL hardware description language description of the taxi circuit automatic billing, plete function simulation of the circuit. In the design process, focus on the taxi automatic billing and circuit design divided into functional modules. Then, a preliminary study of the principles of integrated circuit logic, the software automatically billing for a taxi to the logic integrated circuit. Finally, the use of experimental development of EDA system to download and verify the circuit. Validation results show that the automatic billing taxi designed to plete the desired circuit function. Key words ultrahighspeed integrated circuit hardware description language, counters, Quartus II , highspeed integrated circuits 目錄 摘要……………………………………………………………………2序言……………………………………………………………………5第一章EDA與QuartusII開發(fā)系統(tǒng)介……………………………………6 EDA發(fā)展況……………………………………………………………………6 硬件描述語VHDL…………………………………………………………….7 VHDL的簡介……………………………………………………………….7 VHDL的流程設(shè)計………………………………………………………….7 QuartusII 軟件操作流程……………………………………………………8第二章 課題概述………………………………………………………………10 出租車計費系統(tǒng)的實驗任務(wù)及求……………………………………………10 、出租車計費系統(tǒng)的原理和方案計……………………………………………10 、具體的方案計…………………………………………………………………11………………………………………………………….11………………………………………………………………12第三章 硬件路…………………………………………………………………13 時鐘電路………………………………………………………………………13 555電路………………………………………………………………………13…………………………………………………………………………14………………………………………………………………………15……………………………………………………………………15第四章 計費系統(tǒng)的VHDL計………………………………………………15 分頻器…………………………………………………………………………16 標(biāo)志模塊………………………………………………………………………17 等待模塊………………………………………………………………………19 計程模塊………………………………………………………………………21 計費模塊………………………………………………………………………24 譯碼模塊………………………………………………………………………28第五章 總程序的設(shè)計及其實現(xiàn)的結(jié)果………………………………30