【正文】 哈爾濱工程大學(xué)專業(yè) 碩士學(xué)位論文 I 摘要 無(wú)陀螺捷聯(lián) 導(dǎo)慣性航 導(dǎo)航系統(tǒng)（ GFSINS）是指舍棄陀螺儀而直接把加速度計(jì)安裝在載體上，通過(guò)對(duì)加速度計(jì)輸出的 比力 信號(hào)進(jìn)行解算從而得到導(dǎo)航參數(shù)的慣性導(dǎo)航系統(tǒng)。捷聯(lián)慣導(dǎo)系統(tǒng)同平臺(tái)式慣導(dǎo)系統(tǒng)相比具有可靠性高、壽命長(zhǎng)、節(jié)省體積空間等優(yōu)點(diǎn)。無(wú)陀螺捷聯(lián)慣導(dǎo)系統(tǒng)因?yàn)樯釛壛送勇輧x，與有陀螺的捷聯(lián)慣導(dǎo)系統(tǒng)相比具有低成本、低功耗、反應(yīng)速度快、動(dòng)態(tài)范圍大等優(yōu)點(diǎn)。隨著深亞微米技術(shù)的出現(xiàn)，現(xiàn)場(chǎng)可編程邏輯門(mén)陣列（ FPGA）得到了迅猛發(fā)展，也使得可編程片上系統(tǒng)（ SOPC）成為未來(lái)嵌入式系統(tǒng)設(shè)計(jì)技術(shù)發(fā)展的必然趨勢(shì) [1]。 本論文根 據(jù) 以九加速度計(jì)為配置方案的 無(wú)陀螺捷聯(lián)導(dǎo)航計(jì)算機(jī)的特點(diǎn)和應(yīng)用要求，提出了基于 FPGA 的無(wú)陀螺捷聯(lián)慣性導(dǎo)航系統(tǒng)的硬件設(shè)計(jì)方案。 系統(tǒng)主要 包括數(shù)據(jù)采集模塊和數(shù)據(jù)解算模塊 兩部分 。數(shù)據(jù)采集模塊由 STM32 負(fù)責(zé)控制兩片 AD7656 將 9 個(gè) 加速度計(jì)輸出的模擬信號(hào)轉(zhuǎn)換為數(shù)字信號(hào) 。 數(shù)據(jù)解算模塊采用 Altera 公司的 FPGA 芯片，利用 SOPC 技術(shù) 完成 FPGA 內(nèi)部硬件邏輯的構(gòu)建 ，核心算法由高性能 32 位 Nios II 處理器完成 ，實(shí)現(xiàn)了浮點(diǎn)運(yùn)算 。 最后完成了原理圖和 PCB 設(shè)計(jì)，研制了 實(shí)驗(yàn) 樣機(jī) ，為無(wú)陀螺捷聯(lián)慣性導(dǎo)航系統(tǒng)的進(jìn)一步研究工作奠定了 基礎(chǔ)。 關(guān)鍵詞 ： GFSINS；導(dǎo)航計(jì)算機(jī)； FPGA； SOPC； STM32； 雙口 RAM 哈爾濱工程大學(xué)專業(yè) 碩士學(xué)位論文 II Abstract Gyroscope Free Strapdown Inertial Navigation System(GFSINS) is a kind of Inertial Navigation System, accelerometers are derectly fixed in the carrier without using gyroscope. So acceleration is the exclusive in formation source, we can get all the navigation parameters by puting. Compared with The Platformtype Inertial Navigation System The Strapdown Inertial Navigation System is high reliability, longevity, small volume and so on. Compared with Strapdown Inertial Navigation System with gyroscope, GFSINS is low cost, low power, promote reaction, wide dynamic range and so on. With the emergence of submicron technology, FPGA chips have bee more and more popular, thus making the system on a programmable chip (SOPC) design the mainstream technique in embedded system design field. Take the features and application requirements of gyroscope free strapdown inertial navigation system with nine accelerometers into consideration, the thesis put forward a hardware design scheme of gyroscope free strapdown inertial navigation puter based on FPGA. The system includes data acquisition module and data decoding module two parts. In the data acquisition module, two AD7656 chips will change the analog signals from nine accelerometers into digital signals controlled by STM32. In the data decoding module, the internal hardware logic of FPGA is constructed by SOPC technology. The key algorithm is acplished by highperformance 32bit processor Nios II, in which realized the floating point arithmetic. Finally, the principle chart and PCB design is finished, making a test model, laying the foundation for the further research work of GFSINS. Keywords： GFSINS； Navigation puter； FPGA； SOPC； STM32； DPRAM 哈爾濱工程大學(xué)專業(yè) 碩士學(xué)位論文 III 目錄 摘要 ............................................................................................................................... I Abstract ........................................................................................................................ II 第 1章 緒論 ................................................................................................................ 1 慣性導(dǎo)航系統(tǒng)簡(jiǎn)介 ........................................................................................... 1 慣性導(dǎo)航系統(tǒng)的分類 ................................................................................ 1 無(wú)陀螺捷聯(lián)慣導(dǎo)系統(tǒng) ................................................................................ 3 導(dǎo)航計(jì)算機(jī)發(fā)展簡(jiǎn)介 ....................................................................................... 3 論文的意義和主要內(nèi)容 ................................................................................... 4 第 2章 系統(tǒng)總體設(shè)計(jì)方案 ........................................................................................ 6 無(wú)陀螺捷聯(lián)慣導(dǎo)系統(tǒng)的工作原理 ................................................................... 6 導(dǎo)航計(jì)算機(jī)的整體工作流程 ........................................................................... 7 導(dǎo)航計(jì)算機(jī)的性能要求 ............................................................................ 8 核心器件的選型 ............................................................................................... 8 加速度計(jì)選型 ............................................................................................ 8 A/D 芯片選型 ........................................................................................... 10 雙口 RAM IDT 7133 ............................................................................... 13 微控制器選型 .......................................................................................... 15 FPGA 選型 ................................................................................................ 16 本章小結(jié) ......................................................................................................... 17 第 3章 數(shù)據(jù)采集模塊 .............................................................................................. 18 加速度計(jì)硬件連接設(shè)計(jì) ................................................................................. 18 加速度計(jì)調(diào)理電路 ......................................................................................... 19 減法電路 .................................................................................................. 19 低通濾波電路 .......................................................................................... 20 AD7656 管腳連接設(shè)計(jì) ................................................................................... 21 基于雙口 RAM 的雙 CPU通訊電路 ............................................................ 24 采集系統(tǒng)的供電電源設(shè)計(jì)方案 ..................................................................... 25 +5V到 5V電壓轉(zhuǎn)換電路 ....................................................................... 26 +5V到 .................................................................... 27 集成開(kāi)發(fā)環(huán)境介紹 ......................................................................................... 27 哈爾濱工程大學(xué)專業(yè) 碩士學(xué)位論文 IV Real View MDK 簡(jiǎn)介 ............................................................................... 27 ? Vision IDE ............................................................................................ 28 本章小結(jié) .....................................................................