【正文】 畢 業(yè) 設 計（論 文） 題目： 等精度數字頻率計 的設計 Title: Equal Precision Frequency Meter Plan 姓 名 ： 梁 森 專 業(yè) ： 電子信息工程 學 號 ： 07061234 指導教師 ： 陳 堅 二 零 一 一 年 六 月東華理工大學畢業(yè)設計（論文） 摘要 I 摘 要 頻率檢測是電子測量領域的最基本也是最重要的測量 之一。頻率信號抗干擾能力強、易于傳輸，可以獲得較高的測量精度，所以測頻率方法的研究越來越受到重視。本課題的等精度數字頻率計設計，采用當今電子設計領域流行的 EDA 技術，以 CPLD 為核心，配合 AT89C51 單片機，采用多周期同步測頻原理，實現了 信號頻率的等精度頻率測量，此外，該系統還可以測方波信號寬度及高、低電平的占空比。 基于傳統測頻原理的頻率計的測量精度將隨著被測信號頻率的下降而降 低，在實用中有很大的局限性，而等精度頻率計不但有 較 高的測量精度，而且在整個測頻區(qū)域內保持恒定的測試精度。運 用等精度測量原理，結合單片機技術設計了一種數字頻率計，由于采用了屏蔽驅動電路及數字均值濾波等技術措施，因而能在較寬定的頻率范圍和幅度范圍內對頻率，周期，脈寬，占空比等參數進行測量，并可通過調整閘門時間預置測量精度。選取的這種綜合測量法作為數字頻率計的測量算法，提出了基于 CPLD 的數字頻率計的設計方案。給出了該設計方案的實際測量效果，證明該設計方案切實可行，能達到較高的頻率測量精度。 設計中用一塊復雜可編程邏輯器件 CPLD(Complex Programmable Logic Device)芯片 EPM7128SLC8415 完成各種時序邏輯控制、計數功能。在 Quartus II 平臺上，用 VHDL 語言編程完成了 CPLD 的軟件設計、編譯、調試、仿真和下載。用AT89C51 單片機作為系統的主控部件，實現整個電路的測試信號控制、數據運算處理、鍵盤掃描和控制數碼管的顯示輸出。系統將單片機 AT89C51 的控制靈活性及 CPLD 芯片的現場可編程性相結合，不但大大縮短了開發(fā)研制周期，而且使本系統具有結構緊湊、體積小，可靠性高，測頻范圍寬、精度高等優(yōu)點。 關鍵詞 等精度測量 ； 單片機 ； 頻率計 ； 閘門時間 東華理工大學畢業(yè)設計（論文） ABSTRACT II ABSTRACT In the field of electronic measurement, the frequency checking is one of mostfundamental and critically important measuring methods. Because frequency signal, whichis easily transported, has strong resistance to the disturbance and can be measured withhigh precision, research on the method by measuring frequency have more and moresignificance in the real application. Along with is measured based on the traditional frequency measurement principle frequency meter measuring accuracy the signalling frequency the drop but to reduce, in is practical has the very big limitation, but and so on the precision frequency meter not only has teaches the high measuring accuracy, moreover maintains the constant test precision in the entire frequency measurement region. Using and so on the precision survey principle, unified the monolithic integrated circuit technical design one kind of numeral frequency meter, because has used the shield actuation electric circuit and technical measure and so on digital average value filter, thus could in pared in the frequency range and the scope scope which the width decided to the frequency, the cycle, the pulse width, occupied parameter and so on spatial ratio carries on the survey, and might through the adjustment strobe time initialization measuring accuracy. Selection this kind of synthesis measured the mensuration took the digital frequency meter the survey algorithm, proposed based on the CPLD digital frequency meter design proposal. Has produced this design proposal actual survey effect, proved this design proposal is practical and feasible, can achieve the high frequency measurement precision. During the design, a chip EPM7128SLC84_1 S in CPLD fulfills timing logic control and count function. Under the flat of Quartus II， through VHDL language CPLD software design } pilation } debug, simulation and download can be carried out. By use of the AT89C51 single chip puter as the main controlling parts, the AT89C51 realizes test signal control keyboard scan and output display of LED. 東華理工大學畢業(yè)設計（論文） ABSTRACT III The system bines the control flexibility of AT89C51 with programmable performance of CPLD， so not only can it shorten the period of the development and research， but also has the advantages of pact structure little volume high reliability wide scope and high precision. Keywords： Precision survey。 monolithic integrated circuit。 frequency meter, strobe tim 東華理工大學畢業(yè)設計（論文） 目錄 1 目 錄 摘 要 ............................................................................................................................. I ABSTRACT .................................................................................................................. II 第一章 緒 論 ............................................................................................................ 1 背景 ..................................................................................................................... 1 研究內容及相關技術 ......................................................................................... 1 測量原理 ............................................................................................................. 2 第二章 總體設計思路 ............................................................................................... 3 多周期同步測量方法 ......................................................................................... 3 等精度測量原理 ................................................................................................. 3 設計要求 ............................................................................................................. 6 第三章 硬件電路設計 ............................................................................................... 6 系統頂層電路設計 ............................................................................................. 6 設計總體思路及原理 ......................................................................................... 7 CPLD 的結構與功能介紹 ............................................................................ 7 等精度數字頻率計項目設計 方案 ................................................................... 7 等精度數字頻率計的設計 .......................................................................... 7 等精度數字頻率計主要由以下幾個部分組成 .......................................... 8 系統的基本工作方 式如下 .......................................................................... 9 CPLD/FPGA 測頻