【正文】 aELSIF datat=2 THEN data ELSIF datat=3 THEN dataELSIF datat=4 THEN dataELSIF datat=5 THEN dataELSIF datat=6 THEN dataELSIF datat=7 THEN dataELSIF datat=8 THEN dataELSIF datat=9 THEN dataELSIF datat=10 THEN dataELSIF datat=11 THEN dataELSIF datat=12 THEN dataELSIF datat=13 THEN dataELSIF datat=14 THEN dataELSE dataEND IF。WHEN set_addram2=rsdataWHEN diaplay_cgrom=rsIF datat=0 THEN dataELSIF datat=1 THEN dataELSIF datat=2 THEN dataELSIF datat=3 THEN dataELSIF datat=4 THEN dataELSIF datat=5 THEN dataELSIF datat=6 THEN dataELSIF datat=7 THEN dataELSIF datat=8 THEN dataELSIF datat=9 THEN dataELSIF datat=10 THEN dataELSIF datat=11 THEN dataELSIF datat=12 THEN dataELSIF datat=13 THEN dataELSIF datat=14 THEN dataELSE dataEND IF。END CASE。end if。when “01”=elsif sint =“01”thenCASE state ISWHEN clear_display= rsWHEN set_initial=IF datatELSIF datat=3 THEN rsELSIF datat=4 THEN rsELSE rsEND IF。WHEN set_cgram=rsdataIF num END IF。WHEN write_cgram= rsdata IF datat=8 THEN num:=num+1。datat:=0。state IF num =7 THEN num:=0。t:=“00000000”。stateEND IF。END IF。WHEN set_addram1=rsdataWHEN diaplay_cgram=rsif sint=“00”thenIF datat=0 THEN dataELSIF datat=1 THEN dataELSIF datat=2 THEN data ELSIF datat=3 THEN dataELSIF datat=4 THEN dataELSIF datat=5 THEN dataELSIF datat=6 THEN dataELSIF datat=7 THEN dataELSIF datat=8 THEN dataELSIF datat=9 THEN dataELSIF datat=10 THEN dataELSIF datat=11 THEN dataELSIF datat=12 THEN dataELSIF datat=13 THEN dataELSIF datat=14 THEN dataELSE dataEND IF。WHEN set_addram2=rsdataWHEN diaplay_cgrom=rsIF datat=0 THEN dataELSIF datat=1 THEN dataELSIF datat=2 THEN dataELSIF datat=3 THEN dataELSIF datat=4 THEN dataELSIF datat=5 THEN dataELSIF datat=6 THEN dataELSIF datat=7 THEN dataELSIF datat=8 THEN dataELSIF datat=9 THEN dataELSIF datat=10 THEN dataELSIF datat=11 THEN dataELSIF datat=12 THEN dataELSIF datat=13 THEN dataELSIF datat=14 THEN dataELSE dataEND IF。END CASE。end if。when others =null。end case。END IF。end process。END fwm。Choice41library ieee。use 。use 。程序包 entity choice4_1 is定義實體 port(s:in std_logic_vector(1 downto 0)。信號選擇端口s d1,d2: in std_logic_vector(7 downto 0)。d1d2d3d4分別連接四個波形發(fā)生模塊y: out std_logic_vector(7 downto 0))。定義輸出信號端口 end choice4_1。architecture behav of choice4_1 is結構體 beginprocess(s)begincase s iscase when語句進行信號位的選擇when “01”=ywhen “11”=ywhen others=null。end case。end process。進程結束 end behav。結構體結束fangbolibrary ieee。use 。use 。use 。entity fangbo is port(clkf,rf:in std_logic。qf:out std_logic_vector(7 downto 0))。end entity。architecture behav of fangbo is signal a:bit。begin process(clkf,rf)計數(shù)分頻variable t:integer range 0 to 256。begin if(rf=39。039。)then aqfsinlibrary ieee。use 。use 。use 。entity sin is port(clksin,rsin:in std_logic。da:out BIT_vector(7 downto 0))。end entity。architecture behav of sin is signal a:bit。begin process(clksin,rsin)計數(shù)分頻 variable t:integer range 0 to 256。begin if(rsin=39。039。)then avariable tmp:std_logic_vector(7 downto 0)。variable d:BIT_vector(7 downto 0)。beginif a=39。039。 thend:=“00000000”。elsif clksin39。event and clksin=39。139。 then if a39。event and a=39。139。 then if tmp=“00111111” then tmp:=“00000000”。else tmp:=tmp+1。end if。case tmp is when “00000000”=d:=“11111111”。when “00000001”=d:=“11111110”。when “00000010”=d:=“11111100”。when “00000011”=d:=“11111001”。when “00000100”=d:=“11110101”。when “00000101”=d:=“11101111”。when “00000110”=d:=“11101001”。when “00000111”=d:=“11100001”。when “00001000”=d:=“11011001”。when “00001001”=d:=“11001111”。when “00001010”=d:=“11000101”。when “00001011”=d:=“10111010”。when “00001100”=d:=“10101110”。when “00001101”=d:=“10100010”。when “00001110”=d:=“10010110”。when “00001111”=d:=“10001010”。when “00010000”=d:=“01111100”。when “00010001”=d:=“01100000”。when “00010010”=d:=“01100011”。when “00010011”=d:=“01010111”。when “00010100”=d:=“01001011”。when “00010101”=d:=“01000000”。when “00010110”=d:=“00110101”。when “00010111”=d:=“00101011”。when “00011000”=d:=“00100010”。when “00011001”=d:=“00011010”。when “00011010”=d:=“00010011”。when “00011011”=d:=“00001101”。when “00011100”=d:=“00001000”。when “00011101”=d:=“00000001”。when “00011110”=d:=“00000001”。when “00011111”=d:=“00000000”。when “00100000”=d:=“00000000”。when “00100001”=d:=“00000001”。when “00100010”=d:=“00000001”。when “00100011”=d:=“00001000”。when “00100100”=d:=“00001101”。when “00100101”=d:=“00010011”。when “00100110”=d:=“00011010”。when “00100111”=d:=“00100010”。when “00101000”=d:=“00101011”。when “00101001”=d:=“00110101”。when “00101010”=d:=“01000000”。when “00101011”=d:=“01001011”。when “00101100”=d:=“01010111”。when “00101101”=d:=“01100011”。when “00101110”=d:=“01100000”。when “00101111”=d:=“01111100”。when “00110000”=d:=“10001001”。when “00110001”=d:=“10010110”。when “00110010”=d:=“10100010”。when “00110011”=d:=“10101110”。when “00110100”=d:=“10111010”。when “00110101”=d:=“11000101”。when “00110110”=d:=“11011001”。when “00110111”=d:=“11011001”。when “00111000”=d:=“11100001”。when “00111001”=d:=“11101001”。when “00111010”=d:=“11101111”。when “00111011”=d:=“11110101”。when “00111100”=d:=“11111001”。when “00111101”=d:=“11111100”。when “00111110”=d:=“11111110”。when “00111111”=d:=“11111111”。when others=null。end case。end if。da頻率計頻率產生器： library ieee。use 。library lpm。use 。entity lpm_counter0 is port(clock: in std_logic。q: out std_logic_vector(26 downto 0))。end lpm_counter0。architecture syn of lpm_counter0 is signal sub_wire0 : std_logic_vector(26 downto 0)。ponent lpm_counter generic（lpm_direction : string。lpm_port_updown : string。lpm_type : string。lpm_width : natural)。port(clock : in std_logic。q : out std_logic_vector(26 downto 0))。end ponent。begin q “up”，lpm_port_updown = “port_unused”，lpm_type = “l(fā)pm_counter”，lpm_width = 27)port map（clock = clock，q = sub_wire0)。end syn。測頻控制信號發(fā)生器 library ieee。use 。use 。entity testpl is port(clk:in std_log