【正文】 基于 EP1C6Q240C8 的直流電機硬件設(shè)計電路 所有模塊均在里面； 張旭東 2021 年 3 月 18 日 Graduation design Title: DC motor control system based on FPGA hardware design College of physics and Information Engineering Science Institute: Major in electronic information engineering The class number B08073011 School No. 202107301124 Name of student Zhang Xudong Teachers Cao ChangMao The first part: package Figure U21A, U21B, U21C, U21D said the same piece of chip EP1C6Q240C8, has 240 pins, using the PQFP package (Plastic Quad Flat Package, plastic quad flat package ), PQFP packaged chip has peripheral pins, and the pins between distance is very small, pin is also very small, general mass large scale integrated circuit using this form of encapsulation. This form of packaged chip must use SMT ( Surface Mount Technology, SMT chip pins ) on the edge of the board is welded together with. To SMT technology, personal understanding, ., surface mount technology, generally used to weld some pins in the hundreds more chips, such as BGA, PGA generally use this technique。 BGA ball grid array package With the development of integrated circuit technology, the integrated circuit package requirements more stringent. This is because the packaging technology related to product function, when the frequency of IC than 100MHz, traditional package may have a socalled CrossTalk ( crosstalk) phenomenon, and when the IC pin number is greater than 208 Pin, the traditional way of packaging has its difficulties. Therefore, in addition to the use of the QFP package, most high pin count chip ( such as graphics chip and chip group ) is to use BGA ( Ball Grid Array Package ) packaging technology. BGA has bee CPU, motherboard South / Beiqiao chip, high density, high performance, multi pin package best choice. The second part: circuit diagram On the principle of: When we put the schematic ponent library to do a good job after, in principle, to have the principle diagram, we can select the make library option can be generated to be referenced diagram ponents library, we can use automatic number to every module number, can also be manually coded, and then the tools found in footprints Manager tab can be used to check the device package, if it is found that the device was not encapsulated, can be found in the library a and the device number of pins with the same types of chip packaging of the device package package operation。 A, U21A chip is the main part of the: EP1C6Q240C8main part, the part of the pin a little bit more ( described later )。s hard drive, large capacity ) The U21C module represents the chip power supply and grounding If I remember correctly, the general chip is used in TTL level, the level can provide different voltage to meet different needs. The number of electricity which is widely used in. It has14 pins are connected to + , another 12pin connection is + , we can put the power supply part with a capacitor to ground, the benefits of this is to filter out the power of internally generated some highfrequency crosstalk signal, ground part are simulated, some digital ground, so alone up the advantage of preventing signal interference, intermediate with a single inductor to connect, so can hinder the high frequency signal is directly coupled。 The clock signal is temporal logic based, it is used for decision logic unit in the state when the update. The clock signal is a fixed cycle and running the semaphore, the clock frequency ( clock frequency, CF ) is the countdown clock cycle. Clock edge trigger signal means that all state changes have occurred in the edge of the clock arrival time. At the edge of the trigger mechanism, only the rising or falling edge is the effective signal to the control logic unit, a state quantity change. As in the end is a rising edge or the trailing edge as effective trigger signal, depending on the logic design technology. In FPGA and level trigger manner, here is not described, only know. In three, EP1C6Q240C8 on the internal functional ponents: The second part I from schematic perspective to the analysis of this chip, we have the following overall observation of the whole chip A core board based on Altera, EP1C6, Cyclone device embedded system development provides a A very good hardware platform, it provides developers with the following resources: The 1 main chip using Altera Cyclone device EP1C6Q240C8 2EPCS1I8 configuration chip 34 user defined buttons 44 userdefined LED 51seven segment LED code 6 standard AS interface and JTAG debugging interface 7 50MHz high accuracy clock source 8three high density interface 9 system power on reset circuit 10support +5V direct input, board power management module System main chip with240pins, SMD package E1C6FPGA, it has 6030LE, 26M4K RAM (total239616bits ),2 high performance PLL and up to 185 users Custom IO. At the same time, the system can also be based on user demand for the design to replace the other different series Core board, such as: EP1C12, EP2C20, EP3C25 etc.. Therefore, no matter from the performance, Or from the system flexibility, whether you are a beginner, or senior hardware engineer, it will Be your good helper. EP1C6 core board system function frame diagram: FPGA platform provides a wealth of resources for students or developers to learn to use, resource pack The interface munication, control, storage, data conversion and interactive display of several major modules, interface. Communication module includes the SPI interface, IIC interface, VGA interface, RS232 interface, USB interface, PS2 key Disk / mouse interface,1Wire interface。 data The conversion module includes a serial ADC, DAC and audio COD