【正文】 to mand the motor’s movement. For higher end applications that require more calculation power, the move to ARM processors is possible. This creates a highend solution (up to date for the mature markets) Figure Mixedsignal SoC diagram 29 which could last over the application’s lifespan because the microcontroller would be a small part of an integrated circuit that emulates the module’s functionalities. In order to understand how larger geometries can be better suited for some mixedsignal applications, one needs to understand all of the characteristics involved. Below we will discuss seven key characteristics, however this is by no means prehensive. Gate and memory size in mixedsignal applications generally drive cost. Gate and memory size drive cost because most mixedsignal devices are core limited. This can be quite different than an alldigital circuit. Many times, the alldigital device will have so many I/Os that the number of pads on the device determines the periphery and therefore the area. This is rarely the case for mixedsignal devices. For the most part digital cells scale pretty closely to the expected area savings. One would expect a cell to be 51 percent smaller than a cell of equivalent function. This is illustrated by the following formula: % )( )( R a t i o S i z e 22 ??? While this holds for digital cells we will see that analog cells are quite a different story. Therefore the amount of digital content (including memory) is the key in determining the best technology for the application. 2. Parasitic lessens as the geometry decreases. This is good news for both the digital and analog designer. Understandably this will translate into high bandwidths and data rates. While the magnitude of the parasitic capacitance per gate or resistance of the interconnection is most assuredly lower as geometry decreases, it is also less predictable. This can cause analog modeling problems and highlights the need for careful understanding of the parasitic. 3. The transconductance characteristic is the relationship between a drain current and the voltage across the gate and source. As the geometry decreases the transconductance gets higher. This is good news for both analog and digital domains in that smaller conductance interacts with capacitance to create smaller bandwidths and therefore lower data rates. 30 It is well understood that as geometry decreases the voltage limits of the device decrease as well. In the pure digital world this is beneficial in several ways: less power and less radiated emissions. The only downside is the need for multiple voltage rails on most digital circuits. In the analog domain, the power savings is there but reduced range of operation makes the design task harder. It is quite mon for analog designers to bias their circuits at VT + 2Von and Vdd ? (VT + 2Von). Unfortunately, the threshold voltage, VT, does not scale with the geometry. In other words, the operating range of voltages gets smaller as the technology shrinks. This means the analog portions of a circuit must be more tightly controlled which translates to larger, better matched transistors. 4. Channel resistance gets lower as the technology shrinks. While this may sound like a good thing, and for digital circuits it generally is, this translates to transistors with lower gain in the analog domain. Lower gain may mean more stages in the circuit. 5. The linearity of smaller geometries also bees a factor in analog designs. Often nonlinearity problems are solved by increasing the size of the circuit. An example of this can be seen in D/A and A/D converters where the performance of the converter is very much proportional to the size of the circuit. 6. Noise in circuits implemented in smaller technologies can cause problems for analog designers. This is usually worsened by the fact that there is usually a large and fast digital circuit that is generating much of the noise. The smaller operating voltage range works against the designer as well. Signal to noise ratio in the analog circuit gets worse because the signal levels go down but the noise levels may actually go up. 7. Analog circuit modeling in smaller geometries is problematic. Much of this is due to the lower levels of predictability and the nature of the parasitic. Some of it is due to the maturity of the technology as well. This, of course, will improve as the technology develops. 31 Because of these items listed above it is important to understand that as the process geometry shrinks, the analog actually gets bigger, and definitely harder. This has to be pensated by increasing the sizes of the transistors, capacitors and resistors used. Moving to smaller technologies should only be done when the performance requirements of the application demand it. For most mixedsignal SoC devices this will be driven by the digital gate count and the amount of memory in the design. Only when there is significant digital content should you consider smaller technologies. Conclusion The latest generation of mixedsignal process technologies has moved well into the deep submicron world where adding digital circuits and cores to an analog ASIC has bee a costeffective approach. With the addition of digital process capability and the digital processing horsepower that bees available, many analog functions are being converted to digital signals earlier in the signal path. The advantage of this approach is that digital filters and digital control elements are not sensitive to drift inaccuracies caused by aging, process changes or temperature changes. The result is a much more robust design than an analogonly approach. 中文 譯文： 橋接模擬與數(shù)字世界之間的鴻溝 大多數(shù)應用程序要求模擬和數(shù)字功能的并存，把此功能結(jié)合在單一芯片上的好處是很明顯的。此外，數(shù)字和模擬功 32 能往往以不同的速度進行發(fā)展，但混合信