【正文】 he digital processing horsepower that bees available, many analog functions are being converted to digital signals earlier in the signal path. The advantage of this approach is that digital filters and digital control elements are not sensitive to drift inaccuracies caused by aging, process changes or temperature changes. The result is a much more robust design than an analogonly approach. Phaselocked loopA phaselocked loop or phase lock loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input reference signal. It is an electronic circuit consisting of a variable frequency oscillator and a phase detector. This circuit pares the phase of the input signal with the phase of the signal derived from its output oscillator and adjusts the frequency of its oscillator to keep the phases matched. The signal from the phase detector is used to control the oscillator in a feedback loop.Frequency is the derivative of phase. Keeping the input and output phase in lock step implies keeping the input and output frequencies in lock step. Consequently, a phaselocked loop can track an input frequency, or it can generate a frequency that is a multiple of the input frequency. The former property is used for demodulation, and the latter property is used for indirect frequency synthesis.Phaselocked loops are widely employed in radio, telemunications, puters and other electronic applications. They can be used to recover a signal from a noisy munication channel, generate stable frequencies at a multiple of an input frequency (frequency synthesis), or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated circuit can provide a plete phaselockedloop building block, the technique is widely used in modern electronic devices, with output frequencies from a fraction of a hertz up to many gigahertz.Practical analogiesAutomobile race analogyFor a practical idea of what is going on, consider an auto race. There are many cars, and each of them wants to go around the track as fast as possible. Each lap corresponds to a plete cycle, and each car will plete dozens of laps per hour. The number of laps per hour (a speed) corresponds to an angular velocity (. a frequency), but the number of laps (a distance) corresponds to a phase (and the conversion factor is the distance around the track loop).During most of the race, each car is on its own and is trying to beat every other car on the course, and the phase of each car varies freely.However, if there is an accident, a pace car es out to set a safe speed. None of the race cars are permitted to pass the pace car (or the race cars in front of them), but each of the race cars wants to stay as close to the pace car as it can. While it is on the track, the pace car is a reference, and the race cars bee phaselocked loops. Each driver will measure the phase difference (a distance in laps) between him and the pace car. If the driver is far away, he will increase his engine speed to close the gap. If he39。s time to the reference time, he noticed that his clock was too fast. Consequently, he could turn the timing adjust a small amount to make the clock run a little slower. If things work out right, his clock will be more accurate. Over a series of weekly adjustments, the wall clock39。s stability).An early mechanical version of a phaselocked loop was used in 1921 in the ShorttSynchronome clock.Structure and functionPhaselocked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure. Both analog and digital PLL circuits include four basic elements:˙Phase detector,˙Lowpass filter,˙Variablefrequency oscillator, and˙feedback path (which may include a frequency divider).Performance parameters˙Type and order˙Lock range: The frequency range the PLL is able to stay locked. Mainly defined by the VCO range.˙Capture range: The frequency range the PLL is able to lockin, starting from unlocked condition. This range is usually smaller than the lock range and will depend . on phase detector.˙Loop bandwidth: Defining the speed of the control loop.˙Transient response: Like overshoot and settling time to a certain accuracy (like 50ppm).˙Steadystate errors: Like remaining phase or timing error˙Output spectrum purity: Like sidebands generated from a certain VCO tuning voltage ripple.˙Phasenoise: Defined by noise energy in a certain frequency band (like 10kHz offset from carrier). Highly dependent on VCO phasenoise, PLL bandwidth, etc.˙General parameters: Such as power consumption, supply voltage range, output amplitude, etc.ApplicationsPhaselocked loops are widely used for synchronization purposes。s oscillator. Typically, some sort of redundant encoding is used, such as 8b/10b encoding.DeskewingIf a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be received and amplified before it can drive the flipflops which sample the data, there will be a finite, and process, temperature, and voltagedependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this delay is to include a deskew PLL on the receive side, so that the clock at each data flipflop is phasematched to the received clock. In that type of application, a special form of a PLL called a delaylocked loop (DLL) is frequently used.Clock generationMany electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors e from clock generator PLLs, which multiply a lowerfrequency reference clock (usually 50 or 100s clock distribution. The clock distribution is usually balanced so that the clock arrives at every endpoint simultaneously. One of those endpoints is the PLL