用在hcl中表示指令-展示頁
2025-01-30 15:41本頁面
【正文】 ations occur simultaneously at clock rising (except CC) – 7 – Processor SEQ Hardware Key ? Blue boxes: predesigned hardware blocks ? ., memories, ALU ? Gray boxes: control logic ? Describe in HCL ? White ovals: labels for signals ? Thick lines: 32bit word values ? Thin lines: 48 bit values ? Dotted lines: 1bit values Instr uctionm em or yInstr uctionm em or yPCincrem entPCincrem entCCCC A LUA LUD atam em or yD atam em or yNe wPCrBdstE dstMALUAALUBM em .con tr olAdd rsrcA srcBr e a dw r i t eALUf un .Fet chDecodeExecuteM em oryW ri t e backd a t a o u tR egisterfileR egisterfileA BMEBchdstE dstM srcA srcBi cod e i f un rAPCv al C v al Pv al Bv al ADa tav al Ev al MPCne w PC– 8 – Processor Fetch Logic Predefined Blocks ? PC: Register containing PC ? Instruction memory: Read 6 bytes (PC to PC+5) ? Split: Divide instruction byte into icode and ifun ? Align: Get fields for rA, rB, and valC Instr uctionm em or yInstr uctionm em or yPCincrem entPCincrem entrBico de if un rAPCv al C v al PNe edreg id sNe edv al CI nst rv al idA lignA lignS plitS plitBy t es 1 5By t e 0– 9 – Processor Fetch Logic Control Logic ? Instr. Valid: Is this instruction valid? ? Need regids: Does this instruction have a register bytes? ? Need valC: Does this instruction have a constant word? Instr uctionm em or yInstr uctionm em or yPCincrem entPCincrem entrBico de if un rAPCv al C v al PNe edreg id sNe edv al CI nst rv al idA lignA lignS plitS plitBy t es 1 5By t e 0– 10 – Processor Fetch Control Logic pushl rA A 0 rA 8jXX D est 7 fn D estpopl rA B 0 rA 8call D est 8 0 D estrrmovl rA , rB 2 0 rA rBirmovl V , rB 3 0 8 rB Vrmmovl rA , D ( rB ) 4 0 rA rB Dmrmovl D ( rB ), rA 5 0 rA rB DOPl rA , rB 6 fn rA rBret 9 0nop 0 0halt 1 0bool need_regids = icode in { IRRMOVL, IOPL, IPUSHL, IPOPL, IIRMOVL, IRMMOVL, IMRMOVL }。 bool instr_valid = icode in { INOP, IHALT, IRRMOVL, IIRMOVL, IRMMOVL, IMRMOVL, IOPL, IJXX, ICALL, IRET, IPUSHL, IPOPL }
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