用在hcl中表示指令(完整版)
【正文】 4 required functions ? Generates condition code values ? CC ? Register with 3 condition code bits ? bcond ? Computes branch flag Control Logic ? Set CC: Should condition code register be loaded? ? ALU A: Input A to ALU ? ALU B: Input B to ALU ? ALU fun: What function should ALU pute? CCCC A LUA LUAL UAAL UBAL Uf u n .Bchi co d e i f u n v a l C v a l Bv a l Av a l ESe tCCbcon dbcon d– 15 – Processor ALU A Input valE ? valB + –4 Decrement stack pointer No operation valE ? valB + 4 Increment stack pointer valE ? valB + valC Compute effective address valE ? valB OP valA Perform ALU operation OPl rA, rB Execute rmmovl rA, D(rB) popl rA jXX Dest call Dest ret Execute Execute Execute Execute Execute valE ? valB + 4 Increment stack pointer int aluA = [ icode in { IRRMOVL, IOPL } : valA。 1 : RNONE。 – 11 – Processor Decode amp。 1 : RNONE。t need ALU ]。t need address ]。 1 : valP。 ]。 – 23 – Processor SEQ Hardware (Review) ? Stages occur in sequence ? One operation in process at a time Instr uctionm em or yInstr uctionm em or yPCincrem entPCincrem entCCCC A LUA LUD atam em or yD atam em or yNe wPCrBdstE dstMALUAALUBM em .con tr olAdd rsrcA srcBr e a dw r i t eALUf un .Fet chDecodeExecuteM em oryW ri t e backd a t a o u tR egisterfileR egisterfileA BMEBchdstE dstM srcA srcBi cod e i f un rAPCv al C v al Pv al Bv al ADa tav al Ev al MPCne w PC– 24 – Processor Instruct ionm em oryInstruct ionm em oryPCinc rem entPCinc rem entCCCCA LUA LUDatam em oryDatam em oryPCrBdst E dst MALUAALUBM em .c ont rolAddrsrcA srcBr e a dw r i teALUf un.Fet chDeco deExec ut eM em or yW r i t e bac kd a ta o u tRegi sterfi leRegi sterfi leA BMEBc hdst E dst M srcA srcBicode if un rApBc h pValM pValC pValPpI c odePCv alC v alPv alBv alADat av alEv alMPCSEQ+ Hardware ? Still sequential implementation ? Reorder PC stage to put at beginning PC Stage ? Task is to select PC for current instruction ? Based on results puted by previous instruction Processor State ? PC is no longer stored in
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