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【正文】 In addition to emulation, two plementary approaches to design verification are simulation and model checking, a type of formal verification. Simulation applies vectors to a software model of a design and checks to sec if the output has the correct value. The approach is straightforward, but is being increasingly tortuous as designs bee more plicated and the number of possible test vectors mushrooms. So recently, electronic design automation panies have been turning to model checking to prove that designs are correctly done. The sticking point with model checking is its great difficulty of use. It is not for most engineers, said Simon Napper, chief operating officer OF Innologic Systems Inc., San Jose, Calif. The usage model is very difficultit checks properties. But the designer isn39。s plex ICs are tough to design, they are very much tougher to verify. A variety of tools are available, each with its pros and cons. Emulation translates a design into fieldprogrammable gate arrays (FPGAs). Presumably, if the array works as planned, the final chip will also. The emulation platform also enables designers to try 0111 the software that will run on the ASIC. The approach, though, is slow. Typical emulation systems run at a few megahertz. At roughly one million cycles per second, designers arc not getting ough performance out of their emulation systems to verify or understand some of the things that are going on with video generation or high bandwidth munications, said John Gallagher, director of marketing for Synplicity Inc., Sunnyvale, Calif. They must process a large number of operations to ensure their functionality is correct, he added. The reason that emulation systems are so slow, according to Gallagher, is that they route the design through many FPGAs and many boards. Simplicity solution is to use a few highend FPGAs having over one million gates running at 100 MHz. Typically, a million FPGA gates translates into 200 000 ASIC gates. Putting nine such chips on a board in a threebythree array allows designers to represent up to ASlC gates. And routing delays are greatly curtailed because each chip is no more than two hops away from any other chip in the array. The pany% product, called Certify, is not intended to pete with reconfigurable emulation systems, which are very effective at debugging designs during the internal design process, explained Gallagher. Rather, it is a true prototype of the system, running at speeds that may approach the real thing. Certify handles three fundamental operations, said Gallagher. The first is partitioning, or breakings up the ASIC register transfer level (RTL) code into different FPGAs. It does synthesis, turning the RTL code into ASIC gates equivalent to the final ASIC gates. Then it does timing analysis. We haven39。s correctness is fast being more arduous than doing the design itself. And finally, not only gate counts but chip frequencies also are climbing, so that getting a design to meet its timing requirements without too many design iterations is a receding goal. As is the wont of the electronic design automation (EDA) munity, these concerns are being attacked by startup panies led by a few individuals with big ideas and a little seed money.PARLEZVOUS SUPERLOG?A system on a chip prises both circuitry and the software that runs on it. Such a device may contain an embedded processor core running a software modem. Most often, after the chip39。VHDL language。B 翻譯原文Electronic design automationKeyword EDA。 IC。 FPGAPROCESS DESCRIPTION Three obstacles in particular bedevil ic designers in this dawn of the system on a chip. The first is actually a shortfallthe hardware and software ponents of the design lack a unifying language. Then, as the number of logic gates per chip passes the million marks, verification of a design39。s functionality is spelled out, usually on paper, the hardware potent is handed off to the circuit designers and the software is given to the pro grammars, to meet up again at some later date. The part of the chips functionality that will end up as logic gates and transistors is writ ten in a hardware design languageVirology or VHDL, while the part that will end up as software is most often described in the programming language C or C++. The use of these disparate languages hampers the ability to describe, model, and debug the circuitry o
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