【正文】 They must process a large number of operations to ensure their functionality is correct, he added. The reason that emulation systems are so slow, according to Gallagher, is that they route the design through many FPGAs and many boards. Simplicity solution is to use a few highend FPGAs having over one million gates running at 100 MHz. Typically, a million FPGA gates translates into 200 000 ASIC gates. Putting nine such chips on a board in a threebythree array allows designers to represent up to ASlC gates. And routing delays are greatly curtailed because each chip is no more than two hops away from any other chip in the array. The pany% product, called Certify, is not intended to pete with reconfigurable emulation systems, which are very effective at debugging designs during the internal design process, explained Gallagher. Rather, it is a true prototype of the system, running at speeds that may approach the real thing. Certify handles three fundamental operations, said Gallagher. The first is partitioning, or breakings up the ASIC register transfer level (RTL) code into different FPGAs. It does synthesis, turning the RTL code into ASIC gates equivalent to the final ASIC gates. Then it does timing analysis. We haven39。XV verifies designs written in Virology. EXPCV is meant for custom designs and memory blocks. THE TIME IS RIGHT Though the design of ICs with semiconductor geometries below pm face challenges throughout development, some of the biggest hurdles occur during physical design, when the gates are placed on the chip and the interconnects are routed between them Problems occur here for a number of reasons. First, the capacitance, resistance, and inductance of the interconnects cannot be ignored, as they were in older, larger technologies. Crosstalk between interconnects。 Web sites. The issue, according to Michael Bitzko, president of the pany, is that designers of products based on there ponents need to be able to obtain information about them quickly and route it to their engineering, manufacturing, and procurement departments as quickly as possible. In a nutshell,” said Bitzko, people used to take weeks to get data sheets. Then along cane the Web and PDFformatted documents. But in order to create, ray, schematic symbols and footprints fur printed circuit boards, information from PDF documents must often be reentereda costly and timeconsuming process when time to infarct is a concern. 39。首先就是缺乏一些東西即設(shè)計(jì)的硬件部件與軟件部件之間缺少統(tǒng)一的語言。 由于已長期研究電子設(shè)計(jì)自動化，對于這方面的關(guān)注經(jīng)常受到一些新建的公司抨擊。通常，芯片的功能被寫在紙上后，硬件部件就交給了集成電路設(shè)計(jì)者，軟件部件就給了程序設(shè)計(jì)者，在以后的某個閘門在合起來組在一起。 從工業(yè)角度上看我們相信是時候推出一種新的設(shè)計(jì)語言處理硬件和軟件的問題，使系統(tǒng)從最初的設(shè)計(jì)規(guī)格直達(dá)最后的檢驗(yàn)。davidmann說一種設(shè)計(jì)語言必須滿足三個需求。沒有一種現(xiàn)存的方法滿足這些需求，于是davidmann和flake決定發(fā)明一種新的協(xié)同設(shè)計(jì)語言，并命名為superlog。從C和Java方面superlog又集成了動態(tài)處理器和其他軟件編制。公司已經(jīng)開始和不同標(biāo)準(zhǔn)的組織合作工作達(dá)到其推廣的目的。沖向終點(diǎn)的比賽并不是每一個人都相信我們需要新的語言。他們也希望他們的平臺能成為實(shí)際的標(biāo)準(zhǔn)。kunkel告訴IEEE spectrum說大部分軟件開發(fā)者用C++且系統(tǒng)開發(fā)者已經(jīng)運(yùn)用C++在行為級上描述他們的系統(tǒng)。例如，位向量0和1的字符串，和所有的在其上將實(shí)行的操作。但據(jù)KUNEL說，system C的合成工具將在用戶群體中得出一個語言上被廣泛接受的自然結(jié)果。每一種可使用的工具都有其缺點(diǎn)和優(yōu)勢。然而走勢很緩慢。據(jù)Gallagher說仿真系統(tǒng)之所以運(yùn)行緩慢是由于要使設(shè)計(jì)按部就班的運(yùn)行需要通過許多現(xiàn)場可編程門陣列和許多板。將九個這樣的芯片以33陣列放置在板上。”然而，它卻真的是系統(tǒng)的藍(lán)本，高速運(yùn)行可能使目標(biāo)更真實(shí)。此時做時間分析。模擬是在一種設(shè)計(jì)和檢驗(yàn)的軟件模型上應(yīng)用向量，查看輸出是否有正確的值。加州圣荷西innologic系統(tǒng)公司操作部經(jīng)理simon napper說“并非大多數(shù)工程師能夠使用它。這是一個verilog模擬裝置除了沒有通過邏輯發(fā)送1和0，這種工具傳送符號或帶有二進(jìn)制數(shù)值的符號。象征性模擬能完全檢驗(yàn)的電路，僅使用正規(guī)檢驗(yàn)的話對其復(fù)雜性有限制。這樣從一個32位降至16位的乘數(shù)。EXPCV則意在用戶定制設(shè)計(jì)和存儲塊。首先，連接體的電容，電阻和感應(yīng)系數(shù)不能被忽視。由加州Sunnyvale的monterey設(shè)計(jì)系統(tǒng)公司提出的方案稱為全球設(shè)計(jì)技術(shù)。（多數(shù)放置和運(yùn)行工具按順序分析每一種系統(tǒng)規(guī)定參數(shù)的流程圖?；旧险f，這種方法首先確定時序，然后調(diào)整信元大小以滿足時間的需要。該公司是一個虛擬企業(yè)，總部設(shè)在馬薩諸塞州的萬寶路。他說“簡而言之，人們過去用幾周的時間去得到數(shù)據(jù)單表。這樣就使得基于網(wǎng)絡(luò)的文件比傳統(tǒng)的HTML有更多的功能。該公司計(jì)劃在今年第一季度上市一個產(chǎn)品。ott進(jìn)一步闡述說”我們還有一個免費(fèi)的網(wǎng)絡(luò)定位服務(wù)器，在此人們運(yùn)用netmeeting和一個網(wǎng)絡(luò)板可以提出問題并找到解決答案。該公司的產(chǎn)品websim是一個網(wǎng)絡(luò)瀏覽器和仿真器的接口程序。 transim公司和供應(yīng)商合作建立部件模型，這樣設(shè)計(jì)者門可以注冊供應(yīng)商的網(wǎng)站選擇他們電源供應(yīng)所需的零部件，進(jìn)入組建或測試環(huán)境，在線運(yùn)行仿真器。花費(fèi)極小，每個用戶低至10美元。仿真器在transim公司的六個服務(wù)器中的大農(nóng)場中運(yùn)行，其中六個服務(wù)器由sun microsystems公司提供。websim允許設(shè)計(jì)者使用仿真器在網(wǎng)絡(luò)上模擬設(shè)計(jì)。 基于網(wǎng)絡(luò)的電子設(shè)計(jì)的其他方面從事起來要比設(shè)計(jì)和信息管理方面進(jìn)展緩慢。，旨在展示這項(xiàng)技術(shù)的用途。quickdata服務(wù)器是為查找電子部件信息的參數(shù)查詢引擎，而quickdata轉(zhuǎn)換器則是將包含在PDF數(shù)據(jù)表中的信息轉(zhuǎn)換成可用的格式。但是為了創(chuàng)造圖表式的符號和覆蓋區(qū)為覆蓋電路板，PDF文件中的信息必須頻繁重新輸入，這是一項(xiàng)耗資巨大且非常浪費(fèi)時間的過程，而且時間對于市場來說非常重要。 ，從提供者的網(wǎng)址上我們可以看到關(guān)于集成電路，芯片和電路板的信息。網(wǎng)絡(luò)上的電子設(shè)計(jì)自動化 當(dāng)已經(jīng)成立的電子設(shè)計(jì)自動化公司正在努力解決如何在生產(chǎn)線中利用網(wǎng)絡(luò)這個問題時，一些更小更靈敏的公司和一些剛剛起步的公司則致力于創(chuàng)新產(chǎn)品和服務(wù)上，主要在設(shè)計(jì)管理領(lǐng)域創(chuàng)新。對于位于加州cupertino的正在開發(fā)Blast Fusion結(jié)構(gòu)設(shè)計(jì)系統(tǒng)的Magma設(shè)計(jì)自動化公司來說，時序收斂是重中之重。第一個包含這項(xiàng)技術(shù)的產(chǎn)品是去年四月生產(chǎn)的Dolphin。由于在一起更為緊密，必須控制連接體之間的串?dāng)_。當(dāng)門被放置到芯片上時，連接體在它們之間運(yùn)行?！眎nnologic公司已經(jīng)發(fā)行了兩個版本的象征性模擬?！袄缫粋€模擬檢驗(yàn)器將不停的旋轉(zhuǎn)運(yùn)行但從不產(chǎn)生一個結(jié)果。為了說明和完全檢驗(yàn)一個四位微機(jī)芯片的加法器，需要256個二元向量，運(yùn)行256個模擬周期?！?