【正文】 f the IC and the software in a coherent fashion.It is time, many in the industry believe, for a new design language that can cope with both hardware and software from the initial design specification right through to final verification. Just such a new language has been developed by CoDesign Automation Inc., San Jose, Calif. Before launching such an ambitious enterprise, cofounders Simon Davidmann, who is also chief operating officer, and Peter Flake ruled out the usefulness of extending an existing language to meet systemonchip needs. Among the candidates for extension were C, C++, Java, and Verilog. A design language should satisfy three requirements, maintained Davidmann. It should unify the design process. It should make designing more efficient. And it should evolve out of an existing methodology. None of the existing approaches filled the bill. So Davidmann and Flake set about developing new codesign language called Superlog. A natural starting point was a blend of Virology and C since from an algorithm point of view, a lot of Virology is built on C, explained Davidmann. Then they spiced the blend with bits and pieces of VHDL and Java. From Virology and VHDL, Superlog has acquired the ability to describe hardware aspects of the design, such as sequential, binatorial, and multivalued logic. From C and Java it inherits dynamic processes and other software constructs. Even functions like interfaces, protocols, and state machines, which till now have often been done on paper, can be described in the new language. To support legacy code written in a hardware description or programming language, Superlog allows both Virology and C modules to be imported and used directly.It is important for the language to be in the public domain, according to Davidmann. The pany has already begun to work with various standards organizations to this end. Not to be overlooked is the need for a suite of design tools based on the language. Recently CoDesign identified a number of electronic design automation panies, among them Magma Design Automation, Sente, and Viewlogic, that will develop tools based on Superlog. CoDesign will also develop products for the front end of the design process.ARACE TO THE FINISH Not everyone is convinced that a new language is needed. SystemC, a modeling platform that extends the capabilities and advantages of C/C++ into the hardware domain has been proposed as an alternative. Such large and powerful panies as Synopsys, Coware, Lucent Technologies, and Texas Instruments have banded together under the Open SystemC Initiative to promote their version of the nextgeneration design platform. To get SystemC off to a running start, the group offers a modeling platform for download off their Web site free of charge. Their hope is also to make their platform the de facto standard. The rationale for developing SystemC was straightforward, according to Joachim Kunkel, general manager and vice president of the System Level Design Business Unit at Synopsys. It was to have a standard language in which semiconductor vendors, IP vendors, and system houses could exchange systemlevel IP and executable specifications, and the electronic design automation industry could develop interoperable tools. Supporters of SystemC believe that the wouldbe standard has to be based on C++ because it allows capabilities to be added to it without leaving the language standard, Kunkel told JEEE Spectrum. Most software developers use C++ and many systems developers use C++ already to describe their systems at a behavioral level. But till now it has not been possible to describe hardware using the language.The developers of SystemC have solved that problem by defining new C++ class libraries and a simulation kcrne1 that bring to C++ all of the capabilities needed to describe hardware. These new classes implement new functionality, explained Kunkel. For example, bit vectorsstrings of zeros and onesand all the operations that you would do on them. The SystemC developers also provided a class of signed and unsigned numbers, the notion of a signal, and other concepts needed to model hardware. There are still some holes, however. For example, it is still not possible to synthesize a gatelevel netlist from a SystcmC description. Rut synthesis tools for SysteniC would he a natural result of broad acceptance of the language within the