【正文】 during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation, ALE is emitted at a constant rate of 1/6the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALEdisable bit has no effect if the microcrontroller is in external execution mode.PSENProgram Store Enable is the read strobe to external program memory. When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.Pin Description (Continued)EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. This pin also receives the 12volt programming enable voltage (VPP) during Flash programming when 12volt programming is selected.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifier.Special Function RegistersA map of the onchip memory area called the Special Function Register (SFR) space is shown in Table 1. Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.Timer 2 Registers Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L) arethe Capture/Reload registers for Timer 2 in 16bit capture mode or 16bit autoreload mode.Special Function Registers (Continued)Interrupt Registers The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.Data MemoryThe AT89C52 implements 256 bytes of onchip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space. When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space.AT89C52主要性能參數(shù)：l 與MCS51產(chǎn)品指令和引腳完全兼容l 8K字節(jié)可重復檫寫FLASH閃速存儲器l 1000次檫寫周期l 全靜態(tài)操作：0HZ24HZl 三級加密程序存儲器l 256X8字節(jié)內(nèi)容RAMl 32個可編程I/O口線l 3個16位定時/計數(shù)器l 8個中斷源l 可編程串行UART通道l 低功耗空閑和掉電模式功能特性概述：AT89C52提供以下標準功能：8K字節(jié)閃速存儲器，256字節(jié)內(nèi)部RAM，32個I/O口線，3個16位定時/計數(shù)器，一個6向量兩極中斷結構，一個全雙工串行通信口，片內(nèi)振蕩器及時鐘電路。 Eight Interrupt Sources 32 Programmable I/O Lines ThreeLevel Program Memory Lock 8 Kbytes of InSystem Reprogrammable Flash MemoryEndurance: 1,000 Write/Erase Cycles最后，對所有在這三年年里的學習和生活中，給予我各種關心我?guī)椭娜藗?，我僅表達我最衷心的謝意！謝謝你們！參 考 文 獻1 余永權. ATMEL89系列單片機應用技術[M]. 北京：北京航空航天大學出版社.2 2002 數(shù)碼語音芯片、產(chǎn)品及應用電路資料匯編[M]. 3 劉欣，等. IDS語音器件分段地址的獲取[J]. 電子技術應用，1999（10）4 5 《MCS51單片機接口技術與運用》李華 北京航天航空大學出版社6 《單片機接口技術與運用》胡漢才 清華大學出版社7 周航慈. 單片機應用程序設計技術（修訂版）[M]. 北京：北京：北京航空航天大學出版社，8 《單片微型機原理`應用與實驗，第三版》張友德 等編 復旦大學出版社AT89C52資料：Features衷心地謝謝您，張老師！同時，我還要感謝電子實驗室的楊旭楊老師，無論是從資料上，還是從經(jīng)驗和技術上都提供了極大的幫助。在畢業(yè)設計的這段時間中，李老師不僅使我在學業(yè)上有了很大的提高，而且言傳身教，使我學到了作為一名大學生所應具備的那種踏實勤懇、一絲不茍、認真求實的優(yōu)良品質(zhì)和學習作風。等待語音段結束信號TURN2: JNB ,TURN2 ；等待EOM信號的上升沿 RET致 謝在兩個多月的課題研究及論文撰寫過程中，我非常感謝我的導師—張冀祥老師。若A=5放第五段 CLR CLR CALL SOUNDPBACK: RETSOUND: CLR ；/CE端形成一負脈沖啟 NOP 。若A=3放第三段 CLR CLR CALL SOUND JMP PBACKPNEX3: CJNE A,4,PNEX4 MOV P1,60H 。若A=1放第一段 CLR CLR CALL SOUND JMP PBACKPNEX1: CJNE A,2,PNEX2 MOV P1,20H 。調(diào)查找播放地址子程 CJNE R0,5,OUT MOV R0,2FHOUT: RETFIND: MOV A,R0 。放音起始地址送R0LOOP1: JB ,LOOP1 LCALL PLAY 。置放音狀態(tài) MOV P1,00H 。/CE端為低，開始錄音 JNB ,$ SETB RET放音源程序： BEGIN: SETB 。送字段4起始地址 CLR CLR LCALL RECORD JMP BACKNEXT4: CJNE R7,5,BACK MOV R7,00H MOV P1,80H 。送字段2起始地址 CLR CLR