【正文】 s M9K has a very suitable structure for the implementation of shift register. It can work in shift register mode as shown in FigA [11], where w is the data width, m is the length of each segment of shift register and n is the taps. All these three parameters can be set in the Shift Register RAMBased (ALTSHIFT_TAPS) macroblock Altera provided. By adjusting the bination of w, m, n, the macroblock can pletes the shift register function efficiently with one or more M9K controlled by a small amount of LEs. Compared with the traditional shift register, Shift Register RAMBased can only output w X n bits data in n taps while the traditional shift register can output all the wx n x m bits data each clock. For the folded DMF only need W x n bits data outputted by shift register, so it39。 , length of code sequence as N , the search for all the possible phases of code can be finished in the time of NTc . Compared with DMFs, the mode of sliding correlation needs a time of NTc for the searching of every possible code phase, and it needs the time of N2r。s output is given by:y(t) =s(t) * h(t) (2)The filter39。 FPGA1 IntroductionGPS has been widely used in the area of military and civilian at present. Its applications in some special fields set high requirements for the Time To First Fix (TTFF) [1]. For shortening the TTFF, the quick acquisition of PNcode turns to be of great importance. The approaches to the acquisition of PNcode are as follows [24]: sliding correlation, DMF, Fast Fourier Transform (FFT), DMF+FFT . Sliding correlation is sample for implementation, but the serial searching is too slow for quick acquisition. DMF and FFT modes can make a parallel search in the code phase domain. And DMF+FFT is the fastest searching mode now, which makes a parallel search in both code phase domain and frequent domain. From the above we can find that the DMF play an important role in the acquisition of PNcode for the searching of code phase domain. But its consumption of resources is numerous pares with the mode of sliding correlation. So, it39。 RAMbased shift resister。Endmodule英文文獻(xiàn)：Proceedings of ICBNMT20 10OPTIMIZATION AND IMPLEMENTATION OF DIGITAL MATCHED FILTERS BASED ON FPGAZhongliang Deng, Yanpei Yu, Dejun Zou, Weiguo Guan, Lei YangSchool of Electronic Engineering, Beijing University of Posts and Telemunications, Beijing, ChinayuyanpeibuptAbstractThis paper introduces the principal of digital matched filters (DMFs), and based on Field Programmable Gate Array (FPGA), we make an analysis and optimization of DMFs which used in the quick acquisition of PseudoNoise (PN)code for Global Position System (GPS). A structure as Random Access Memory (RAM)based shift register + folded DMF is given in this paper. Compared with traditional folded DMF, this structure utilizes the rich resources of Onchip RAM in FPGA chip to decrease the consumption of Logic Elements (LEs) in FPGA chip. With this structure, the valuable resources of LEs in FPGA chip are saved. Throughout the pilation and the timing simulation by Quartus II, we prove that the structure we proposed can acquire PNcode effectively and be reasonable in saving LEs as the implementation of DMF based on FPGA. This design of DMF can be used in GPS receivers or other Code Division Multiple Access (CDMA) receIvers. Keywords: DMF。 jieduan jieduan( .clk(SYSCLK_BUFOUT), .rst(RST), .datain(datain), .dataout(dataout))。wire clken。 wire rst。 fill fill( .ND(ND), .RDY(RDY), .CLK(SYSCLK_BUFOUT), .RFD(RFD), .DIN(Data_buf), .DOUT(datain))。wire [15 : 0] Data_out。wire CLK。wire ND。 chuanbin chuanbin( .AUDIO_BCLK(BCLK), .rst(RST), .AUDIO_LRCOUT(LRCOUT), .AUDIO_DOUT(DOUT), .Data_Buf(Data_buf), .FIFO_W() )。spi_top spi_top( // Wishbone signals .wb_clk_i(clk_3), .wb_rst_i(~rst_out), .wb_adr_i(wb_adr), .wb_dat_i(wb_wdb), .wb_dat_o(wb_rdb), .wb_sel_i(wb_sel), .wb_we_i(wb_we), .wb_stb_i(wb_stb), .wb_cyc_i(wb_cyc), .wb_ack_o(wb_ack), .wb_err_o(), .wb_int_o(), // SPI signals .ss_pad_o(cs), .sclk_pad_o(SCL), .mosi_pad_o(SDA), .miso_pad_i(miso_pad_i) )。saa_rom rom( .addr(r_rom_rab), .clk(clk_3), .dout(r_rom_rdb) )。 PLL pll( .CLKIN_IN(SYSCLK), .RST_IN(~RST), .CLKDV_OUT(clk_3), .CLKIN_IBUFG_OUT(SYSCLK_BUFOUT), .CLK0_OUT(), .LOCKED_OUT() )。//assign AUDIO_DOUT=DOUT。 assign AMODE=1。 assign miso_pad_i=1。 wire AUDIO_DIN。 wire [4:0] r_rom_rab。 wire miso_pad_i。 wire wb_cyc。 wire wb_we。 wire [31:0] wb_rdb。 wire [4:0] wb_adr。 wire rst_out。 inout SCL,SDA。 //數(shù)字音頻接口ADC方向的幀信號(hào) output DIN。//數(shù)字音頻接口ADC方向的數(shù)據(jù)輸出 input LRCIN。 input BCLK。附錄頂層文件：module Aic23_top(SYSCLK,RST,BCLK,DOUT,LRCIN,LRCOUT,DIN,ACS,AMODE,SCL,SDA)。在兩個(gè)多月的日子里，還要感謝眾位學(xué)長姐、同學(xué)的共同幫助，與你們一同的學(xué)習(xí)和研究讓我有了更大的進(jìn)步，你們的陪伴讓兩個(gè)月的研究生活變得絢麗多彩。并且感謝老師不厭其煩的指出我研究中的缺失，總能在我迷惘時(shí)為我解惑。通過此次畢業(yè)設(shè)計(jì)，我學(xué)到了很多了關(guān)于FPGA和數(shù)字信號(hào)處理方面的知識(shí)，并對(duì)硬件設(shè)計(jì)有了更深刻的思考：對(duì)于一個(gè)研究設(shè)計(jì)一定要有一個(gè)系統(tǒng)性的思維，將每一個(gè)細(xì)節(jié)都放到整個(gè)工程中去思考，同時(shí)應(yīng)多參考各種書籍和相關(guān)研究拓寬自己的思路，最重要的是一定要保持著自信、樂觀的心態(tài)，在設(shè)計(jì)研究過程中肯定會(huì)出現(xiàn)很多問題，只有保持著自信的心態(tài)，多問，多學(xué)才能解決問題。本課題研究的數(shù)字濾波器通過MATLAB的FDATOOL工具獲取了數(shù)字濾波器的系數(shù)，并分析比較了帶通濾波器的幅頻響應(yīng)、相頻響應(yīng)、零極圖等內(nèi)容。結(jié)論經(jīng)過兩個(gè)月的研究設(shè)計(jì)，數(shù)字濾波器的設(shè)計(jì)已經(jīng)達(dá)到了預(yù)期的性能要求。下面分析比較了1KHz和10KHz正弦波濾波前后的頻譜圖：圖522 1KHz正弦信號(hào)濾波前頻譜圖圖523 10KHz正弦信號(hào)濾波前頻譜圖當(dāng)信號(hào)發(fā)生器產(chǎn)生的正弦波加載到FPGA開發(fā)板后，濾除的波形的頻譜如圖所示：圖524 1KHz正弦信號(hào)濾波后頻譜圖圖525 10KHz正弦信號(hào)濾波后頻譜圖并用MATLAB分別對(duì)5KHz和10KHz的正弦信號(hào)通過濾波器前后做了仿真，得到的結(jié)果與硬件實(shí)現(xiàn)的結(jié)果做了對(duì)比，由于量化誤差和器件靈敏度誤差，使得FPGA開發(fā)板得到的結(jié)果與MATLAB仿真得到的結(jié)果存在些許誤差。具體電路如下圖所示： 圖517 FPGA硬件連接示意圖用信號(hào)發(fā)生器分別產(chǎn)生1KHz和10KHz的正弦信號(hào)，首先比較一下濾波前后的時(shí)域波形：圖518 1KHz正弦信號(hào)濾波前時(shí)域波形圖519 10KHz正弦信號(hào)濾波前時(shí)域波形圖520 1KHz正弦信號(hào)濾波后時(shí)域波形圖521 10KHz正弦信號(hào)濾波后時(shí)域波形在整個(gè)設(shè)計(jì)過程中，為了保證工程輸入輸出時(shí)鐘同步，將FIR IP核的輸出28位截取了高16位作為濾波后輸出，因此1KHz濾波后的時(shí)域波形與原波形比存在著誤差。