基于tms320vc5402的語音信號采集系統(tǒng)設(shè)計(參考版)
2025-06-21 16:07本頁面
【正文】 VC5402的強大信號處理能力使得系統(tǒng)能夠?qū)崿F(xiàn)復雜的信號處理算法, 不僅可以進行數(shù)據(jù)采集還能夠?qū)Σ杉盘栠M行算法處理。DMSDI = dst_page。DMSBA = DMSRCP_SUBADDR。DMSDI = dmsefc。 /* Write to DMA src subbank register with increment */DMSDI = dst_addr。 fr reg */,unsigned int dmmcr /*IN: Value to set mode control reg */,unsigned int dmctr /*IN: Value to set element count reg */,unsigned int src_page /*IN: Value to set source page reg */,unsigned int src_addr /*IN: Value to set source addr reg */,unsigned int dst_page /*IN: Value to set dest page reg */,unsigned int dst_addr /*IN: Value to set dest addr reg */){DMSBA = (channel * 5) + DMSRC_SUBADDR。DMPREC = dmpre。DMSDI = dmgcr。DMSDI = dmgsa。DMSDI = dmfri0。DMSDI = dmidx0。 /* Set DMA SubBank Address Register */DMSDI = dmsrcp。= 0xFF00u。 /*DMGCR*/DMSDI = 0x0000u。 /*DMGSA*/DMSDI = 0x0000u。 /*DMFRI0*/DMSDI = 0x0000u。 /*DMIDX0*/DMSDI = 0x0000u。 /*DMSRCP*/DMSDI = 0x0000u。 //mcr}DMSBA = DMSRCP_SUBADDR。 //ctrDMSDI = 0x0000u。 //srcDMSDI = 0x0000u。channel = 4。DMSBA = DMSRC_SUBADDR。 }/* DMA Reset All */static inline void dma_reset_all( void ){unsigned short channel。PRD(port) = 0xffffu。TCR(port) amp。}define TIMER_HALT(port)TCR(port) |= (0x1u TSS)define TIMER_START(port)TCR(port) = (TCR(port) amp。define INTR_GLOBAL_ENABLEasm(\tRSBX INTM)define INTR_CLR_FLAG(flag){IFR |= (0x1u flag)。 0xFF00u) | value。數(shù)據(jù)處理程序：define DSYNC_REVT1 0x05 /* sync to McBSP1 receive event */define AUTOINIT_ENABLE 0x01 /* autoinitialization mode is enabled */define DINM_ENABLE 0x01 /* DMA interrupt is enabled */define IMOD_HALFBLOCK 0x01 /* DMA Int occurs each half block*/define CTMOD_DEC 0x00 /* Decrement counter mode*/define INDEXMODE_NOMOD 0x00 /* No modify (Index mode)*/define INDEXMODE_INC 0x01 /* Post increment index mode*/define HIGH_PRIORITY 0x01 /* Highest priority for DMA channel */define INTSEL_01 0x01 /*RINT0,XINT0,RINT2,XINT2,DMAC2,DMAC3, *//* DMAC4,DMAC5 */define DSYNC_XEVT1 0x06 /* sync to McBSP1 transmit event*/define IMOD_BLOCK 0x00 /* DMA Int occurs at the end of the block*/define CTMOD_DEC 0x00 /* Decrement counter mode*/define SPACE_DATA 0x01 /* DMA Data Space Select*//* MemoryMapped Register Definitions */define DMPREC (*(volatile unsigned int*)(0x0054u))define DMSBA (*(volatile unsigned int*)(0x0055u))define DMSDI (*(volatile unsigned int*)(0x0056u))define DMSDN (*(volatile unsigned int*)(0x0057u))define IMR (*(volatile unsigned int*)(0x0000u))define IFR (*(volatile unsigned int*)(0x0001u))define XPC (*(volatile unsigned int*)(0x001eu))define PMST (*(volatile unsigned int*)(0x001du))define BSCR (*(volatile unsigned int*)(0x0029u))define DRR1_ADDR(port) (port ? 0x41 : 0x21)define DXR1_ADDR(port) (port ? 0x43 : 0x23)define TCR_ADDR(port) (port ? 0x32 : 0x26)define TCR(port) (*(volatile unsigned int*)TCR_ADDR(port))define PRD_ADDR(port) (port ? 0x31 : 0x25)define PRD(port) (*(volatile unsigned int*)PRD_ADDR(port))/* Sub Address Register Definitions */define DMSRC_SUBADDR 0x00define DMDST_SUBADDR 0x01define DMCTR_SUBADDR 0x02define DMSEFC_SUBADDR 0x03define DMMCR_SUBADDR 0x04define DMSRCP_SUBADDR 0x1Edefine DMDSTP_SUBADDR 0x1Fdefine DMIDX0_SUBADDR 0x20define DMIDX
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