【正文】 the data path itself, including an ALU and some registers, the RAM and ROM memories. This original version of the 8051 microcontroller implements 25 instructions and uses 116 latches and 1075 LCs in a FLEX10K20 FPGA device. The clock frequency for this implementation is MHz. In terms of permanent faults, an atspeed selftestable version of this microcontroller has been implemented by inserting in each block a specific builtin selftest structure . The goal now is to modify the finite state machine flipflops, registers and memory blocks of the available VHDL description so that the whole microprocessor bees tolerant to transient faults due to the radiation effects. . Fault Tolerance Technique The technique used in this work to detect and correct faults in memory cells is to assign a Hamming code to each memory element, and to perform the verification of the stored code every time this element is accessed. Since the implemented strategy concerning error recovery is pletely binational, it can be used for any subcircuit (memory block or internal register). In order to implement the Hamming code, two binational ponents were described in VHDL and inserted into the original description of 8051. The first ponent receives an nbit data and returns an mbit coded word (m = n +_log2 n .) The second ponent receives an mbit word and returns an nbit decoded and corrected data. 沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計（ 外文翻譯 ） 18 The same ponents models for coding and decoding used in the memory were used to protect registers in the data path. Now, other instances of those models are used to code and decode ALU registers and accumulator, the stack pointer, the program counter, the instruction register, etc. Each time a register is accessed, it is decoded (and possibly corrected) before being used while the new data is coded before being stored. Since coding and decoding operations are pletely binational, there is no difference in terms of machine cycles needed for the execution of operations in the protected registers. This means the fault tolerant 8051 remains pletely patible with the original version in terms of timing. Of course, the clock frequency is altered, as it will be shown in Section . Fig. 5 shows the scheme of a protected register in the data path. . Synthesis of the Fault Tolerant 8051 The use of presently available highdensity programmable circuits such as Field Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs) is an attractive approach to fast prototyping and cost reduction. Indeed, these circuits can replace a high number of logic ponents allowing to build up plex designs on a single chip in a short developing time. The use of reprogrammable FPGAs along with the possibility to obtain the FPGA programming from high level language descriptions (such as VHDL) offers a flexible and low cost mean to pare the performances of different implementations for a given circuit. In order to validate the implemented structures, the faulttolerant VHDL description was synthesized in a FPGA environment. Although some results related to the synthesis for FPGAs are not absolute, this environment is very useful for fast validation of the technique itself in terms of fault coverage and effectiveness. The 8051’s description with the FSM, the internal RAM and registers tolerant to transient faults, was synthesized in the ALTERA FPGA environment . Table 3 shows the parative results in terms of number of flipflops, area overhead, and clock frequency for each block of the description and for the whole microprocessor. The extra number of latches represents the extra bits necessary for the Hamming code in each memory cell. From Table 3 it can be pointed out that the area overhead for this first implementation is of 64% for a plete faulttolerant microprocessor. Although this can be considered a 沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計（ 外文翻譯 ） 19 penalty, this is lower than replication techniques, while assuring the same or even better protection. Besides, as will be shown later, this is not the minimum possible area overhead. In terms of performance, the pletely fault tolerant 8051 presents only a minor penalty if pared to the original version ( MHz pared to MHz, respectively). Indeed, since the protection blocks are pletely binational, only minor delays are inserted .VHDL simulations have shown that even in the presence of a fault in the protected registers, the microprocessor provides a correct result for a program execution. 5. Hardened Prototype Implementation After the accurate definition of the sensitive parts of the 8051 microprocessor, and the implementation and validation of protection schemes for those blocks, the next step is to implement a physical device to be validated in a real radiation environment. The goal is to include this fault tolerant 8051 version in the THESIC daughter board and expose it to radiation . A FPGA prototype is being proposed in this work to run this last experiment. 6. Conclusion and Future Work We hav。 a control part that provides some control signals for the data path。 result errors。 2) by ground testing using electron beams。 design level, where logic structures are modified to achieve the SEU immunity。機密位只能通過整片擦除的方法清除。 模式 程序存儲器 ALE PSEN P0 P1 P2 P3 閑散模式 內(nèi)部 1 1 數(shù)據(jù) 數(shù)據(jù) 數(shù)據(jù) 數(shù)據(jù) 閑散模式 內(nèi)部 1 1 浮空 數(shù)據(jù) 地址 數(shù)據(jù) 掉電模式 外部 0 0 數(shù)據(jù) 數(shù)據(jù) 數(shù)據(jù) 數(shù)據(jù) 掉電模式 外部 0 0 數(shù)據(jù) 數(shù)據(jù) 數(shù)據(jù) 數(shù)據(jù) 程序存儲器的加密 AT89C51 可 使用對芯片上的三個加密位 LB1， LB2， LB3 進(jìn)行編程（ P）或不編程（ U）得到如下表所示的功能： 程序加密位 保護(hù)類型 1 U U U 沒有程序保護(hù)功能 2 P U U 禁止從外部程序存儲器中執(zhí)行 MOVC 指令讀取內(nèi)部程序存儲器的內(nèi)容 3 P P U 除上表功能外，還禁止程序校驗 4 P P P 除以上功能外，同時禁止外部執(zhí)行 沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計（ 外文翻譯 ） 6 當(dāng) LB1 被編程時，在復(fù)位期間， EA 端的電平被鎖存，如果單片機上電后一直沒有復(fù)位，鎖存起來的初始值是一個不確定數(shù)，這個不確定數(shù)會一直保存到真正復(fù)位位置。退出掉電模式的唯一方法是硬件復(fù)位，復(fù) 位后將從新定義全部特殊功能寄存器但不改變 RAM 中的內(nèi)容，在 VCC 恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效切必須保持一定時間以使振蕩器從新啟動并穩(wěn)定