【正文】 he protected registers. This means the fault tolerant 8051 remains pletely patible with the original version in terms of timing. Of course, the clock frequency is altered, as it will be shown in Section . Fig. 5 shows the scheme of a protected register in the data path. . Synthesis of the Fault Tolerant 8051 The use of presently available highdensity programmable circuits such as Field Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs) is an attractive approach to fast prototyping and cost reduction. Indeed, these circuits can replace a high number of logic ponents allowing to build up plex designs on a single chip in a short developing time. The use of reprogrammable FPGAs along with the possibility to obtain the FPGA programming from high level language descriptions (such as VHDL) offers a flexible and low cost mean to pare the performances of different implementations for a given circuit. In order to validate the implemented structures, the faulttolerant VHDL description was synthesized in a FPGA environment. Although some results related to the synthesis for FPGAs are not absolute, this environment is very useful for fast validation of the technique itself in terms of fault coverage and effectiveness. The 8051’s description with the FSM, the internal RAM and registers tolerant to transient faults, was synthesized in the ALTERA FPGA environment . Table 3 shows the parative results in terms of number of flipflops, area overhead, and clock frequency for each block of the description and for the whole microprocessor. The extra number of latches represents the extra bits necessary for the Hamming code in each memory cell. From Table 3 it can be pointed out that the area overhead for this first implementation is of 64% for a plete faulttolerant microprocessor. Although this can be considered a 沈陽(yáng)航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 19 penalty, this is lower than replication techniques, while assuring the same or even better protection. Besides, as will be shown later, this is not the minimum possible area overhead. In terms of performance, the pletely fault tolerant 8051 presents only a minor penalty if pared to the original version ( MHz pared to MHz, respectively). Indeed, since the protection blocks are pletely binational, only minor delays are inserted .VHDL simulations have shown that even in the presence of a fault in the protected registers, the microprocessor provides a correct result for a program execution. 5. Hardened Prototype Implementation After the accurate definition of the sensitive parts of the 8051 microprocessor, and the implementation and validation of protection schemes for those blocks, the next step is to implement a physical device to be validated in a real radiation environment. The goal is to include this fault tolerant 8051 version in the THESIC daughter board and expose it to radiation . A FPGA prototype is being proposed in this work to run this last experiment. 6. Conclusion and Future Work We hav。退出掉電模式的唯一方法是硬件復(fù)位，復(fù) 位后將從新定義全部特殊功能寄存器但不改變 RAM 中的內(nèi)容，在 VCC 恢復(fù)到正常工作電平前，復(fù)位應(yīng)無(wú)效切必須保持一定時(shí)間以使振蕩器從新啟動(dòng)并穩(wěn)定工作。采用外部時(shí)鐘的電路如圖示。在此期間，當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)，這兩次有效的 PSEN 信號(hào)不出現(xiàn)。因?yàn)閮?nèi)部有電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流。片內(nèi)含有 8 位中央處理器和閃爍存儲(chǔ)單元，有較強(qiáng)的功能的 AT89C51 單片機(jī)能夠被應(yīng)用到控制領(lǐng)域中。對(duì)端口寫(xiě) “1”，通過(guò)內(nèi)部的電阻把端口拉到高電平，此時(shí)可作為輸入口。要注意的是：每當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過(guò)一個(gè) ALE 脈沖時(shí)，閃爍存儲(chǔ)器編程時(shí)，這個(gè)引腳還用于輸入編程脈沖。對(duì)外接電容 C1， C2 雖然沒(méi)有十分嚴(yán)格的要求，但沈陽(yáng)航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 4 電容容量的大小會(huì)輕微影響震蕩頻率的高低、震蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性。終止閑散工作模式的方法有兩種，一是任何一條被允許中斷的事件被激活， IDL 被硬件清除，即刻終止閑散工作模式。 and lost of sequence. The first group, tolerated errors, corresponds to those bit flips injected on memory elements whose content is not relevant for the rest of the program execution when the fault occurs. For instance, it can be a register not used after the fault occurrence or a register that will be written after the fault occurrence, thus “erasing” the fault. All injected faults for which expected and obtained program results (the resulting matrix in our case) differ in at least one bit are considered as leading to result errors. Finally, cases where after fault injection, no answer is got from the processor, are classified in the lost of sequence group. These malfunctions are unrecoverable, needing a hardware reset to restart program execution. Tables 1 and 2 summarize the experimental results. For each type of error, the corresponding percentage of the identified consequences at the program execution level is given. Referring to the Table 1, one can note that nearly half (%) of the total number of 沈陽(yáng)航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 16 injected faults caused errors on the results of this application, while only % of them caused the lost of sequence. From the 5784 faults that resulted in errors, % (5700) of them caused bit flips in the internal memory, while only % (84 faults) affected the SFRs. This demonstrates that the internal memory should be protected against SEU faults to get a reliable operation. Furthermore, despite the reduced number of bits on SFRs (Special Function Registers) used in this application (88 bits = 10 8bit registers + PC) pared to those used in the internal memory (944 bits = 108 words for matrices+ 10 words for variables and constants), they resulted in % of lost sequence faults (154 out of 344 faults that caused lost of sequence). This means, undoubtedly, that the protection of the SFRs in this processor is also required. Thus, from this analysis, the internal memory and the SFRs are defined as the sensitive zones of the 8051. 4. Implementing Fault Tolerance in an 8051 Description Considering the results presented in last section, it clearly appears the need for some kind of protection of the microcontroller as a mean to guarantee the reliable operation of the whole system in radiation environments. In this work, the method chosen for protection