【正文】 unter, the instruction register, etc. Each time a register is accessed, it is decoded (and possibly corrected) before being used while the new data is coded before being stored. Since coding and decoding operations are pletely binational, there is no difference in terms of machine cycles needed for the execution of operations in the protected registers. This means the fault tolerant 8051 remains pletely patible with the original version in terms of timing. Of course, the clock frequency is altered, as it will be shown in Section . Fig. 5 shows the scheme of a protected register in the data path. . Synthesis of the Fault Tolerant 8051 The use of presently available highdensity programmable circuits such as Field Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs) is an attractive approach to fast prototyping and cost reduction. Indeed, these circuits can replace a high number of logic ponents allowing to build up plex designs on a single chip in a short developing time. The use of reprogrammable FPGAs along with the possibility to obtain the FPGA programming from high level language descriptions (such as VHDL) offers a flexible and low cost mean to pare the performances of different implementations for a given circuit. In order to validate the implemented structures, the faulttolerant VHDL description was synthesized in a FPGA environment. Although some results related to the synthesis for FPGAs are not absolute, this environment is very useful for fast validation of the technique itself in terms of fault coverage and effectiveness. The 8051’s description with the FSM, the internal RAM and registers tolerant to transient faults, was synthesized in the ALTERA FPGA environment . Table 3 shows the parative results in terms of number of flipflops, area overhead, and clock frequency for each block of the description and for the whole microprocessor. The extra number of latches represents the extra bits necessary for the Hamming code in each memory cell. From Table 3 it can be pointed out that the area overhead for this first implementation is of 64% for a plete faulttolerant microprocessor. Although this can be considered a 沈陽航空工業(yè)學院電子工程系畢業(yè)設計（ 外文翻譯 ） 19 penalty, this is lower than replication techniques, while assuring the same or even better protection. Besides, as will be shown later, this is not the minimum possible area overhead. In terms of performance, the pletely fault tolerant 8051 presents only a minor penalty if pared to the original version ( MHz pared to MHz, respectively). Indeed, since the protection blocks are pletely binational, only minor delays are inserted .VHDL simulations have shown that even in the presence of a fault in the protected registers, the microprocessor provides a correct result for a program execution. 5. Hardened Prototype Implementation After the accurate definition of the sensitive parts of the 8051 microprocessor, and the implementation and validation of protection schemes for those blocks, the next step is to implement a physical device to be validated in a real radiation environment. The goal is to include this fault tolerant 8051 version in the THESIC daughter board and expose it to radiation . A FPGA prototype is being proposed in this work to run this last experiment. 6. Conclusion and Future Work We hav。 design level, where logic structures are modified to achieve the SEU immunity。需要注意的是：當由硬件復位 來終止閑散工作模式時，中央處理器 CPU 通常是從激活空閑模式那條指令的下一條開始繼續(xù)執(zhí)行程序的，要完成內部復位操作，硬件復位脈沖要保持兩個機器周期有效，在這種情況下，內部禁止中央處理器 CPU 訪問片內 RAM，而允許訪問其他端口，為了避免可能對端口產生的意外寫入：激活閑散模式的那條指令后面的一條指令不應是一條對端口或外部存儲器的寫入指令。 IDL 是閑散等待方式，當 IDL=1，激活閑散工作狀態(tài)，單片機進入睡眠狀態(tài)。10PF。 XTAL1：震蕩器反相放大器及內部時鐘發(fā)生器的輸入端。此外，這個引腳會微弱拉高，單片機執(zhí)行外部程序時，應設置 ALE 無效。 P3 口除了作為一般的 I/O 口外，更重要的用途是它的第二功能，如下表所示： 端口引腳 第二功能 RXD TXD INT0 INT1 T0 T1 WR RD P3 口還接收一些用于閃爍存儲器編程和程序校驗的控制信號。 P2 口 ： P2 口是一個內部帶有上拉電阻的 8 位雙向 I/O 口， P2 的輸出緩沖級可驅動 4 個TTL 電路。作為輸出口時，每一個管腳都能夠驅動 8 個 TTL 電路。沈陽航空工業(yè)學院電子工程系畢業(yè)設計（ 外文翻譯 ） 1 AT89C51 的介紹 （ 原文出處： ： //） 描述 AT89C51 是一個低電壓，高性能 CMOS8 位單片機帶有 4K 字節(jié)的可反復擦寫的程序存儲器（ PENROM）。 引腳描述 VCC：電源電壓 GND：地 P0 口 ： P0 口是一 組 8 位漏極開路雙向 I/O 口，即地址 /數據總線復用口。閃爍編程時和程序校驗時，P1 口接收低 8 位地址。對 P3 口寫如 “1”時，它們被內部電阻拉到高電平并可作為輸入端時，被外部拉低的 P3 口將用電阻輸出電流。這個位置后只有一條MOVX 和 MOVC 指令 ALE 才會被應用。閃爍存儲器編程時，該引腳加上 +12V的編程允許電壓 VPP，當然這必須是該器件是使用 12V 編程電壓 VPP。10PF，而如果使用陶瓷振蕩器建議選擇 40PF177。 PD 是掉電模式，當 PD=1 時，激活掉電工作模式，單片機進入掉電工作狀態(tài)。二是通過硬件復位也可將閑散工作模式終止。 沈陽航空工業(yè)學院電子工程系畢業(yè)設計（ 外文翻譯 ） 7 Description The AT89C51 is a lowpower, highperformance CMOS 8bit microputer with 4K bytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s highdensity nonvolatile memory technology and is patible with the industrystandard MCS51 instruction set and pinout. The onchip Flash allows the program memory to be reprogrammed insystem or by a conventional nonvolatile memory programmer. By bining a versatile 8bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microputer which provides a highlyflexible and costeffective solution to many embedded control applications. Function characteristic The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16bit timer/counters, a five vector twolevel interrupt architecture, a full duplex serial port, onchip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Powerdown Mode saves the RAM contents but freezes the oscilla