【正文】 and lost of sequence. The first group, tolerated errors, corresponds to those bit flips injected on memory elements whose content is not relevant for the rest of the program execution when the fault occurs. For instance, it can be a register not used after the fault occurrence or a register that will be written after the fault occurrence, thus “erasing” the fault. All injected faults for which expected and obtained program results (the resulting matrix in our case) differ in at least one bit are considered as leading to result errors. Finally, cases where after fault injection, no answer is got from the processor, are classified in the lost of sequence group. These malfunctions are unrecoverable, needing a hardware reset to restart program execution. Tables 1 and 2 summarize the experimental results. For each type of error, the corresponding percentage of the identified consequences at the program execution level is given. Referring to the Table 1, one can note that nearly half (%) of the total number of 沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計（ 外文翻譯 ） 16 injected faults caused errors on the results of this application, while only % of them caused the lost of sequence. From the 5784 faults that resulted in errors, % (5700) of them caused bit flips in the internal memory, while only % (84 faults) affected the SFRs. This demonstrates that the internal memory should be protected against SEU faults to get a reliable operation. Furthermore, despite the reduced number of bits on SFRs (Special Function Registers) used in this application (88 bits = 10 8bit registers + PC) pared to those used in the internal memory (944 bits = 108 words for matrices+ 10 words for variables and constants), they resulted in % of lost sequence faults (154 out of 344 faults that caused lost of sequence). This means, undoubtedly, that the protection of the SFRs in this processor is also required. Thus, from this analysis, the internal memory and the SFRs are defined as the sensitive zones of the 8051. 4. Implementing Fault Tolerance in an 8051 Description Considering the results presented in last section, it clearly appears the need for some kind of protection of the microcontroller as a mean to guarantee the reliable operation of the whole system in radiation environments. In this work, the method chosen for protection is the implementation of a faulttolerant version of the 8051 by means of an Error Correcting Code in the sensitive area of the microcontroller (memory and internal 沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計（ 外文翻譯 ） 17 registers, as shown in the last section). The main idea is to provide a VHDL description of the faulttolerant microprocessor that can be synthesized using existent tools. . 8051 Structure The MSC8051 VHDL description presented at was reused to insert radiation tolerant test structures. The original code is entirely patible with the INTEL 8051 microprocessor in terms of instruction timing. As shown in Fig. 3, the microprocessor description is divided into six main blocks: a finite state machine that generates the states and controls the number of cycles for each instruction to guide the circuit operation。為了使單片機(jī)正常工作， 被鎖存的 EA 電平與這個引腳當(dāng)前輯電平一致。終止閑散工作模式的方法有兩種，一是任何一條被允許中斷的事件被激活， IDL 被硬件清除，即刻終止閑散工作模式。 內(nèi)部振蕩電路 外部振蕩電路 閑散節(jié)電模式 AT89C51 有兩種可用軟件編程的省電模式，它們是閑散模式和掉電工作模式。對外接電容 C1， C2 雖然沒有十分嚴(yán)格的要求，但沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計（ 外文翻譯 ） 4 電容容量的大小會輕微影響震蕩頻率的高低、震蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性。需要注意的是：如果加密位 LBI 被編程，復(fù)位時內(nèi)部會鎖存 EA 端狀態(tài)。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲器時將跳過一個 ALE 脈沖時，閃爍存儲器編程時，這個引腳還用于輸入編程脈沖。閃爍編程或校驗時， P2口接收高位地址和其它控制信號。對端口寫 “1”，通過內(nèi)部的電阻把端口拉到高電平，此時可作為輸入口。閑散方式停止中央處理器的工作，能夠允許隨機(jī)存取數(shù)據(jù)存儲器、定時 /計數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。片內(nèi)含有 8 位中央處理器和閃爍存儲單元，有較強(qiáng)的功能的 AT89C51 單片機(jī)能夠被應(yīng)用到控制領(lǐng)域中。 P0 口還能夠在訪問外部數(shù)據(jù)存儲器或程序存儲器時，轉(zhuǎn)換地址和數(shù)據(jù)總線復(fù)用，并在這時激活內(nèi)部的上拉電阻。因為內(nèi)部有電阻，某個引腳被外部信號拉低時會輸出一個電流。當(dāng)震蕩器工作時， RET 引腳出現(xiàn)兩個機(jī)器周期以上的高電平將使單片機(jī)復(fù)位。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲器時，這兩次有效的 PSEN 信號不出現(xiàn)。 時鐘震蕩器 AT89C51 中有一個用于構(gòu)成內(nèi)部震蕩器的高增益反相放大器，引腳 XTAL1 和XTAL2 分別是該放大器的輸入端和輸出端。采用外部時鐘的電路如圖示。在閑散工作模式狀態(tài)，中央 處理器 CPU保持睡眠狀態(tài)，而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。退出掉電模式的唯一方法是硬件復(fù)位，復(fù) 位后將從新定義全部特殊功能寄存器但不改變 RAM 中的內(nèi)容，在 VCC 恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效切必須保持一定時間以使振蕩器從新啟動并穩(wěn)定工作。 2) by ground testing using electron beams。 the data path itself, including an ALU and some registers, the RAM and ROM memories. This original version of the 8051 microcontroller implements 25 instructions and uses 116 latches and 1075 LCs in a FLEX10K20 FPGA device. The clock frequency for this implementation is MHz. In terms of permanent faults, an atspeed selftestable version of this microcontroller has been implemented by inserting in each block a specific builtin selftest structure . The goal now is to modify the finite state machine flipflops, registers and memory blocks of the available VHDL description so that the whole microprocessor bees tolerant to transient faults due to the radiation effects. . Fault Tolerance Technique The technique used in this work to detect and correct faults in memory cells is to assign a Hamming code to each memory element, and to perform the verification of the stored code every time this element is accessed. Since the implemented strategy concerning error recovery is pletely binational, it can be used for any subcircuit (memory block or internal register). In order to implement the Hamming code, two binational ponents were described in VHDL and inserted into the original description of 8051. The first ponent receives an nbit data and returns an mbit coded word (m = n +_log2 n .) The second ponent receives an mbit word and returns an nbit decoded and corrected data. 沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計（ 外文翻譯 ） 18 The same ponents models for coding and decoding used in the memory were used to protect registers in the data path. Now, other instances of those models are used to code and decode ALU registers and accumulator, the stack pointer, the program co