【導(dǎo)讀】和128字節(jié)的存取數(shù)據(jù)存儲(chǔ)器，這種器件采用。片內(nèi)含有8位中央處理器和閃爍存儲(chǔ)單元，有較強(qiáng)的功能的AT89C51單片。機(jī)能夠被應(yīng)用到控制領(lǐng)域中。另外，AT89C51還可以進(jìn)行0HZ的靜態(tài)邏輯操作，并。支持兩種軟件的節(jié)電模式。閑散方式停止中央處理器的工作，能夠允許隨機(jī)存取數(shù)據(jù)。存儲(chǔ)器、定時(shí)/計(jì)數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存隨機(jī)存取數(shù)。據(jù)存儲(chǔ)器中的內(nèi)容，但震蕩器停止工作并禁止其它所有部件的工作直到下一個(gè)復(fù)位。每一個(gè)管腳都能夠驅(qū)動(dòng)8個(gè)TTL電路。當(dāng)“1”被寫(xiě)入P0口時(shí)，每個(gè)管腳都能夠作為。據(jù)總線復(fù)用，并在這時(shí)激活內(nèi)部的上拉電阻。在程序校驗(yàn)時(shí)，輸出指令，需要接電阻。外部數(shù)據(jù)存儲(chǔ)器時(shí)，P2口線上的內(nèi)容在整個(gè)運(yùn)行期間不變。外部程序時(shí)，應(yīng)設(shè)置ALE無(wú)效。XTAL2分別是該放大器的輸入端和輸出端。保持睡眠狀態(tài)，而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。許中斷的事件被激活，IDL被硬件清除，即刻終止閑散工作模式。

　　

【正文】 emory and internal 沈陽(yáng)航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 17 registers, as shown in the last section). The main idea is to provide a VHDL description of the faulttolerant microprocessor that can be synthesized using existent tools. . 8051 Structure The MSC8051 VHDL description presented at was reused to insert radiation tolerant test structures. The original code is entirely patible with the INTEL 8051 microprocessor in terms of instruction timing. As shown in Fig. 3, the microprocessor description is divided into six main blocks: a finite state machine that generates the states and controls the number of cycles for each instruction to guide the circuit operation。 a control part that provides some control signals for the data path。 an instruction part which generates the microcode word for each instruction。 the data path itself, including an ALU and some registers, the RAM and ROM memories. This original version of the 8051 microcontroller implements 25 instructions and uses 116 latches and 1075 LCs in a FLEX10K20 FPGA device. The clock frequency for this implementation is MHz. In terms of permanent faults, an atspeed selftestable version of this microcontroller has been implemented by inserting in each block a specific builtin selftest structure . The goal now is to modify the finite state machine flipflops, registers and memory blocks of the available VHDL description so that the whole microprocessor bees tolerant to transient faults due to the radiation effects. . Fault Tolerance Technique The technique used in this work to detect and correct faults in memory cells is to assign a Hamming code to each memory element, and to perform the verification of the stored code every time this element is accessed. Since the implemented strategy concerning error recovery is pletely binational, it can be used for any subcircuit (memory block or internal register). In order to implement the Hamming code, two binational ponents were described in VHDL and inserted into the original description of 8051. The first ponent receives an nbit data and returns an mbit coded word (m = n +_log2 n .) The second ponent receives an mbit word and returns an nbit decoded and corrected data. 沈陽(yáng)航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 18 The same ponents models for coding and decoding used in the memory were used to protect registers in the data path. Now, other instances of those models are used to code and decode ALU registers and accumulator, the stack pointer, the program counter, the instruction register, etc. Each time a register is accessed, it is decoded (and possibly corrected) before being used while the new data is coded before being stored. Since coding and decoding operations are pletely binational, there is no difference in terms of machine cycles needed for the execution of operations in the protected registers. This means the fault tolerant 8051 remains pletely patible with the original version in terms of timing. Of course, the clock frequency is altered, as it will be shown in Section . Fig. 5 shows the scheme of a protected register in the data path. . Synthesis of the Fault Tolerant 8051 The use of presently available highdensity programmable circuits such as Field Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs) is an attractive approach to fast prototyping and cost reduction. Indeed, these circuits can replace a high number of logic ponents allowing to build up plex designs on a single chip in a short developing time. The use of reprogrammable FPGAs along with the possibility to obtain the FPGA programming from high level language descriptions (such as VHDL) offers a flexible and low cost mean to pare the performances of different implementations for a given circuit. In order to validate the implemented structures, the faulttolerant VHDL description was synthesized in a FPGA environment. Although some results related to the synthesis for FPGAs are not absolute, this environment is very useful for fast validation of the technique itself in terms of fault coverage and effectiveness. The 8051’s description with the FSM, the internal RAM and registers tolerant to transient faults, was synthesized in the ALTERA FPGA environment . Table 3 shows the parative results in terms of number of flipflops, area overhead, and clock frequency for each block of the description and for the whole microprocessor. The extra number of latches represents the extra bits necessary for the Hamming code in each memory cell. From Table 3 it can be pointed out that the area overhead for this first implementation is of 64% for a plete faulttolerant microprocessor. Although this can be considered a 沈陽(yáng)航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 19 penalty, this is lower than replication techniques, while assuring the same or even better protection. Besides, as will be shown later, this is not the minimum possible area overhead. In terms of performance, the pletely fault tolerant 8051 presents only a minor penalty if pared to the original version ( MHz pared to MHz, respectively). Indeed, since the protection blocks are pletely binational, only minor delays are inserted .VHDL simulations have shown that even in the presence of a fault in the protected registers, the microprocessor provides a correct result for a program execution. 5. Hardened Prototype Implementation After the accurate definition of the sensitive parts of the 8051 microprocessor, and the implementation and validation of protection schemes for those blocks, the next step is to implement a physical device to be validated in a real radiation environment. The goal is to include this fault tolerant 8051 version in the THESIC daughter board and expose it to radiation . A FPGA prototype is being proposed in this work to run this last experiment. 6. Conclusion and Future Work We hav