【正文】 易程序及溫度穩(wěn)定性。用戶也可以采用外部時(shí)鐘。 內(nèi)部振蕩電路 外部振蕩電路 閑散節(jié)電模式 AT89C51 有兩種可用軟件編程的省電模式，它們是閑散模式和掉電工作模式。如需要同時(shí)進(jìn)入兩種工作模式，即 PD 和 IDL 同時(shí)為 1，則先激活掉電模式。終止閑散工作模式的方法有兩種，一是任何一條被允許中斷的事件被激活， IDL 被硬件清除，即刻終止閑散工作模式。 掉電模式 在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi) RAM 和特殊功能寄存器的內(nèi)容在中指掉電模式前被凍結(jié)。為了使單片機(jī)正常工作， 被鎖存的 EA 電平與這個(gè)引腳當(dāng)前輯電平一致。 system level, where modifications in the software are performed. In order to avoid SEU , some microprocessor manufacturers such as IBM, are proposing microprocessors in the Silicon on Insulator (SOI) technology. However, this solution is still very expensive. Solutions at the design level, like triple modular redundancy, are widely used to cope with transient errors, especially in random logic. The drawback of this solutions is the resulting area overhead. Error detection and correction techniques (EDAC) have been used in the last few years to increase memories reliability. Examples of these techniques are parity check and Hamming Code . Some studies have shown the capabilities of using error detection and correction in State Machines instead of the use of redundant flipflops with a voter . No previous work was found on protecting a full microcontroller using EDAC techniques. Related works restrict to the use of detection and correction techniques only in internal memories. 3. SEU Effects in the 8051 Microcontroller Several space applications are based on the 8051 microcontroller, because it has a good tradeoff in terms of cost, area occupation, performance and software pliance. In order to implement efficient fault tolerance techniques, a very accurate measure about the localization and the effects of SEU faults in the circuit is necessary. This measure is obtained, in this work, by running controlled fault injection experiments on an existing hardware built on a standard 8051. During the experiments, the microcontroller executes a program designed to provide worst case conditions in terms of exposing the circuit to the effects of SEUs. Indeed, the selected program, a 6 6 matrices multiplication with both the operand and result matrices resident within the 128 byte internal SRAM, occupies most of the internal memory, which constitutes the main target of SEU. 沈陽(yáng)航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 15 . Basic Principles of THESIC Tester Testing integrated circuits in a severe radiation environment prior to their use in operational systems is a mandatory step and will help to reduce the probability of failures in future applications. The sensitivity evaluation of a circuit with respect to radiation can be done: 1) by the analysis of flight data issued from spacecraft operating in the actual environment。 and lost of sequence. The first group, tolerated errors, corresponds to those bit flips injected on memory elements whose content is not relevant for the rest of the program execution when the fault occurs. For instance, it can be a register not used after the fault occurrence or a register that will be written after the fault occurrence, thus “erasing” the fault. All injected faults for which expected and obtained program results (the resulting matrix in our case) differ in at least one bit are considered as leading to result errors. Finally, cases where after fault injection, no answer is got from the processor, are classified in the lost of sequence group. These malfunctions are unrecoverable, needing a hardware reset to restart program execution. Tables 1 and 2 summarize the experimental results. For each type of error, the corresponding percentage of the identified consequences at the program execution level is given. Referring to the Table 1, one can note that nearly half (%) of the total number of 沈陽(yáng)航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 16 injected faults caused errors on the results of this application, while only % of them caused the lost of sequence. From the 5784 faults that resulted in errors, % (5700) of them caused bit flips in the internal memory, while only % (84 faults) affected the SFRs. This demonstrates that the internal memory should be protected against SEU faults to get a reliable operation. Furthermore, despite the reduced number of bits on SFRs (Special Function Registers) used in this application (88 bits = 10 8bit registers + PC) pared to those used in the internal memory (944 bits = 108 words for matrices+ 10 words for variables and constants), they resulted in % of lost sequence faults (154 out of 344 faults that caused lost of sequence). This means, undoubtedly, that the protection of the SFRs in this processor is also required. Thus, from this analysis, the internal memory and the SFRs are defined as the sensitive zones of the 8051. 4. Implementing Fault Tolerance in an 8051 Description Considering the results presented in last section, it clearly appears the need for some kind of protection of the microcontroller as a mean to guarantee the reliable operation of the whole system in radiation environments. In this work, the method chosen for protection is the implementation of a faulttolerant version of the 8051 by means of an Error Correcting Code in the sensitive area of the microcontroller (memory and internal 沈陽(yáng)航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 17 registers, as shown in the last section). The main idea is to provide a VHDL description of the faulttolerant microprocessor that can be synthesized using existent tools. . 8051 Structure The MSC8051 VHDL description presented at was reused to insert radiation tolerant test structures. The original code is entirely patible with the INTEL 8051 microprocessor in terms of instruction timing. As shown in Fig. 3, the microprocessor description is divided into six main blocks: a finite state machine that generates the states and controls the number of cycles for each instruction to guide the circuit operation