【正文】 cells is to assign a Hamming code to each memory element, and to perform the verification of the stored code every time this element is accessed. Since the implemented strategy concerning error recovery is pletely binational, it can be used for any subcircuit (memory block or internal register). In order to implement the Hamming code, two binational ponents were described in VHDL and inserted into the original description of 8051. The first ponent receives an nbit data and returns an mbit coded word (m = n +_log2 n .) The second ponent receives an mbit word and returns an nbit decoded and corrected data. 沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 18 The same ponents models for coding and decoding used in the memory were used to protect registers in the data path. Now, other instances of those models are used to code and decode ALU registers and accumulator, the stack pointer, the program counter, the instruction register, etc. Each time a register is accessed, it is decoded (and possibly corrected) before being used while the new data is coded before being stored. Since coding and decoding operations are pletely binational, there is no difference in terms of machine cycles needed for the execution of operations in the protected registers. This means the fault tolerant 8051 remains pletely patible with the original version in terms of timing. Of course, the clock frequency is altered, as it will be shown in Section . Fig. 5 shows the scheme of a protected register in the data path. . Synthesis of the Fault Tolerant 8051 The use of presently available highdensity programmable circuits such as Field Programmable Gate Arrays (FPGAs) and Programmable Logic Devices (PLDs) is an attractive approach to fast prototyping and cost reduction. Indeed, these circuits can replace a high number of logic ponents allowing to build up plex designs on a single chip in a short developing time. The use of reprogrammable FPGAs along with the possibility to obtain the FPGA programming from high level language descriptions (such as VHDL) offers a flexible and low cost mean to pare the performances of different implementations for a given circuit. In order to validate the implemented structures, the faulttolerant VHDL description was synthesized in a FPGA environment. Although some results related to the synthesis for FPGAs are not absolute, this environment is very useful for fast validation of the technique itself in terms of fault coverage and effectiveness. The 8051’s description with the FSM, the internal RAM and registers tolerant to transient faults, was synthesized in the ALTERA FPGA environment . Table 3 shows the parative results in terms of number of flipflops, area overhead, and clock frequency for each block of the description and for the whole microprocessor. The extra number of latches represents the extra bits necessary for the Hamming code in each memory cell. From Table 3 it can be pointed out that the area overhead for this first implementation is of 64% for a plete faulttolerant microprocessor. Although this can be considered a 沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 19 penalty, this is lower than replication techniques, while assuring the same or even better protection. Besides, as will be shown later, this is not the minimum possible area overhead. In terms of performance, the pletely fault tolerant 8051 presents only a minor penalty if pared to the original version ( MHz pared to MHz, respectively). Indeed, since the protection blocks are pletely binational, only minor delays are inserted .VHDL simulations have shown that even in the presence of a fault in the protected registers, the microprocessor provides a correct result for a program execution. 5. Hardened Prototype Implementation After the accurate definition of the sensitive parts of the 8051 microprocessor, and the implementation and validation of protection schemes for those blocks, the next step is to implement a physical device to be validated in a real radiation environment. The goal is to include this fault tolerant 8051 version in the THESIC daughter board and expose it to radiation . A FPGA prototype is being proposed in this work to run this last experiment. 6. Conclusion and Future Work We hav。 a control part that provides some control signals for the data path。 2) by ground testing using electron beams。機(jī)密位只能通過整片擦除的方法清除。退出掉電模式的唯一方法是硬件復(fù)位，復(fù) 位后將從新定義全部特殊功能寄存器但不改變 RAM 中的內(nèi)容，在 VCC 恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效切必須保持一定時(shí)間以使振蕩器從新啟動(dòng)并穩(wěn)定工作。程序會(huì)首先影響中斷，進(jìn)入中斷服務(wù)程序，執(zhí)行完中斷服務(wù)程序，并緊隨 RETI 指令后，下一條要執(zhí)行沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 5 的指令就是使單片機(jī)進(jìn)入閑散工作模式，那條指令后面的一條指令。在閑散工作模式狀態(tài)，中央 處理器 CPU保持睡眠狀態(tài)，而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。這兩種方式是控制專用寄存器 PCON 中的 PD 和 IDL 位來實(shí)現(xiàn)的。采用外部時(shí)鐘的電路如圖示。如果使用石英晶體，我們推薦電容使用 30PF177。 時(shí)鐘震蕩器 AT89C51 中有一個(gè)用于構(gòu)成內(nèi)部震蕩器的高增益反相放大器，引腳 XTAL1 和XTAL2 分別是該放大器的輸入端和輸出端。如 EA 端為高電平， CPU 則執(zhí)行 內(nèi)部程序存儲(chǔ)器中的指令。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)，這兩次有效的 PSEN 信號(hào)不出現(xiàn)。如果必要，可對(duì)特殊寄存器區(qū)中的 8EH 單元的 D0 位置禁止 ALE 操作。當(dāng)震蕩器工作時(shí)， RET 引腳出現(xiàn)兩個(gè)機(jī)器周期以上的高電平將使單片機(jī)復(fù)位。 P3 口 ： P3 口是一組帶有內(nèi)部電阻的 8 位雙向 I/O 口， P3 口輸出緩沖故可驅(qū)動(dòng) 4 個(gè) TTL電路。因?yàn)閮?nèi)部有電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流。因?yàn)閮?nèi)部有電阻，某個(gè)引 腳被外部信號(hào)拉低時(shí)輸出一個(gè)電流。 P0 口還能夠在訪問外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，轉(zhuǎn)換地址和數(shù)據(jù)總線復(fù)用，并在這時(shí)激活內(nèi)部的上拉電阻。掉電方式保存隨機(jī)存取數(shù)據(jù)存儲(chǔ)器中的內(nèi)容，但震蕩器停止工作并禁止其它所有部件的工作直到下一個(gè)復(fù)位。片內(nèi)含有 8 位中央處理器和閃爍存儲(chǔ)單元，有較強(qiáng)的功能的 AT89C51 單片機(jī)能夠被應(yīng)用到控制領(lǐng)域中。和 128 字節(jié)的存取數(shù)據(jù)存儲(chǔ)器（ RAM），這種器件采用ATMEL 公司的高密度、不容易丟失存儲(chǔ)技術(shù)生產(chǎn)，并且能夠與 MCS51 系列的單片機(jī)兼容。閑散方式停止中央處理器的工作，能夠允許隨機(jī)存取數(shù)據(jù)存儲(chǔ)器、定時(shí) /計(jì)數(shù)器、串行通信口及中斷系統(tǒng)繼續(xù)工作。當(dāng) “1”被寫入 P0 口時(shí)，每個(gè)管腳都能夠作為高阻抗輸入端。對(duì)端口寫 “1”，通過內(nèi)部的電阻把端口拉到高電平，此時(shí)可作為輸入口。對(duì)端口寫 “1”，通過內(nèi)部的電阻把端口拉到高電平，此時(shí)，可作為輸入口。閃爍編程或校驗(yàn)時(shí)， P2口接收高位地址和其它控制信號(hào)。 沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 3 RST： 復(fù)位 輸入。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過一個(gè) ALE 脈沖時(shí)，閃爍存儲(chǔ)器編程時(shí)，這個(gè)引腳還用于輸入編程脈沖。 PSEN： 程序儲(chǔ)存允許輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng) AT89C51 由外部程序存儲(chǔ)器讀取指令時(shí)，每個(gè)機(jī)器周期兩次 PSEN 有效，即輸出兩個(gè)脈沖。需要注意的是：如果加密位 LBI 被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存 EA 端狀態(tài)。 XTAL2：震蕩器反相放大器的輸出端。對(duì)外接電容 C1， C2 雖然沒有十分嚴(yán)格的要求，但沈陽航空工業(yè)學(xué)院電子工程系畢業(yè)設(shè)計(jì)（ 外文翻譯 ） 4 電容容量的大小會(huì)輕微影響震蕩頻率的高低、震蕩器工作的穩(wěn)定性、起振的難