ict測(cè)試原理及程式簡(jiǎn)介(參考版)
2025-05-02 04:57本頁(yè)面
【正文】 TDO Arrows denote access points Basic Test of IC with BoundaryScan Test Data In (TDI) Test Data Out (TDO) ? Do not need to understand the Device Function (Core Logic) ? Scan data in TDI to Output cells. Tester verifies data on outputs. ? Tester applies Data on inputs. Cells capture data on inputs. Data scanned out TDO for verification. The BoundaryScan Test Development Process ? Start with the BSDL file – BSDL means BoundaryScan Description Language” – A language for describing the device specific characteristics of devices – Language subset of VHDL ? Who will write BSDL – ASIC designers – Semiconductor vendors – Test engineers Typical IC with BoundaryScan Test Data In (TDI) Core Logic TMS = Serial Test Clock (TCK) TEST ACCESS PORT CONTROLLER (TAP) 010101010101 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 TMS = Parallel TMS = Parallel Typical IC with BoundaryScan Test Data In (TDI) Core Logic TMS = Serial Test Clock (TCK) TEST ACCESS PORT CONTROLLER (TAP) 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 101010 Thank you! amp。 threshold low 15 high 10000 test pins 2 test pins 3。 threshold low 450 high 10000 ! test pins 7 ! Ground pins mented by IPG test pins 8 … ! test pins 13 !! Test measures 9 test pins 8 test pins 14 ! Fixed pins mented by IPG device “u2” bottom。 threshold low 15 high 10000 test pins 1 test pins 2, 3。 Bar = Num Pins in Range 0 5 10 15 20 25 30 0 to 5 5 to 10 10 to 15 15 to 20 20 to 25 25 to 30 30 to 35 35 to 40 40 to 45 45 to 50 TestJet limit Measurement (in fF) VTEP limit mm pitch 593 Solder Balls pitch 1202 SB TestJET和 VTEP的測(cè)試界限 Aug, 2022 The VTEP/TestJet Verification The TestJet Test default threshold low 20 high 10000 device “u1” test pins 1 test pins 2, 3 test pins 4, 5, 6 ! test pins 7 ! Ground pins mented by IPG test pins 8 … test pins 13 ! test pins 14 ! Fixed pins mented by IPG device “u2” bottom。 iVTEP The VTEP/iVTEP/TestJet Test BGA
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