【正文】 西 安 工 業(yè) 學(xué) 院 畢 業(yè) 論 文 348．3 相關(guān)外文資料翻譯Complete Model of E2PROM Memory Cell for Circuit SimulationAbstractE2PROM memory devices are widely used in embedded applications. For an efficient design flow, a correct modeling of these memory cells in every operation condition bees more and more important, especially due to power consumption limitations. Although E2PROM cells are being used for a long time, very few pact models have been developed. Here，we present a plete pact model based on an original procedure to calculate the floating gate potential in dc conditions, without the need of any capacitive coupling coefficient. This model is designed as a modular structure, so to simplify program/erase and reliability simulations. Program/erase and leakage currents are included by means of simple voltagecontrolled current sources implementing their analytical expression. It can be used to simulate memory cells both during read operation (dc conditions) and during program and erase (transient conditions) giving always very accurate results. We will show also that, provided good description of degradation mechanisms, the same model can be used also for reliability simulations, predicting charge loss due to tunnel oxide degradation.Index TermsCircuit simulation, puter aided design(CAD), integrated circuits, modeling, semiconductor memories.I. INTRODUCTIONIn the semiconductor industry, “modeling” and “characterization” have different meanings. Compact model means an analytic model of the electrical behavior of a circuit element, as used in a SPICElike circuit simulator, and characterization means the procedure by which the parameters of pact model are determined for devices in a particular integrated circuit (IC) manufacturing technology.Compact models should be formulated physically, as functions of both the fundamental process parameters that control device electrical behavior and geometric layout parameters associated with a device (both adjustable layout parameters, such as device length and width 西 安 工 業(yè) 學(xué) 院 畢 業(yè) 論 文 35and technologydependent layout parameters derived from design rules, such as spacing between active areas and implant areas, etc.). There are three main reasons for preferring physically based pact models [1]. First, they provide the best basis for statistical modeling[2]. Second, they provide the best basis for mismatch modeling. Third, during the life cycle of a manufacturing technology there are changes, both in process flow and in design rules, that require to quickly retarget the design library.Although the importance of E2PROM memory cells has grown, very few pact models have been developed to be used in SPACElike simulators [3] to study dc and transient behavior of plex circuits containing E2PROM cells. E2PROM cells are based on floating gate (FG) devices, which are metaloxidesemiconductor (MOS) transistors where a conductive layer is interleaved between gate and channel and it is surrounded by insulator. The conductive layer is called FG. These devices’ threshold voltage can be changed by injecting and/or extracting charge in/from the FG. Because of the lack of reliable pact models in the industry plex circuits are usually simulated replacing FG memory devices with MOS transistors, whose threshold voltage is “manually” changed to simulate the erased and programmed states of the memory cell.Different from pact models proposed in the past [3], [4], the plete pact model of E2PROM cell we have developed is based on an original method to calculate FG potential in dc conditions [5]. This method does not use the fixed capacitive coupling coefficients any more and it is based on the solution of the charge balance equation at the FG node (which improves the FG voltage estimate, ., the overall modeling of the memory device) and on charge equations of the MOS transistor. Moreover, the pact model is designed to be modular, ., any transient phenomena (program, erase, leakage) can be included by adding a voltage controlled current source co。* 鍵盤程序（未完成） 該鍵盤中設(shè)置了三個鍵，用于設(shè)置系統(tǒng)中的調(diào)節(jié)負載輸出變化的參數(shù)。并行驅(qū)動的結(jié)構(gòu)較為簡單，并且在單片機的選擇上，采用了 AT89C51，它有 32 條 I/O 口線，采用并行驅(qū)動方式，接口完全夠用。* 顯示部分的硬件設(shè)計 （未完成）LED 顯示器中的發(fā)光二極管共有兩種連接方法，本方案采用共陽極接法。在使用 RS—485 總線時，如果簡單地按常規(guī)方式設(shè)計電路，在實際工程中可能有通信數(shù)據(jù)收發(fā)的可靠性問題。* RS—485標準通訊口串行通信接口是指設(shè)備之間的接口。* X5043/45 接口芯片在該系統(tǒng)中，為解決電源開斷、瞬時電壓不穩(wěn)等不安全因素，將會造成系統(tǒng)死機、信息丟失、運行不穩(wěn)定等故障，實現(xiàn)系統(tǒng)安全可靠、穩(wěn)定、實時運行，故采用 X5045 芯片。通過在單塊芯片上組合通用的 CPU 和 Flash 存儲器。此項畢業(yè)設(shè)計囊括了專業(yè)電工、電子、電力電子技術(shù)，MCS—51 系列單片機工作原理及應(yīng)用技術(shù)， PROTEL 技術(shù)等學(xué)科知識。對設(shè)計中遇到的問題,會虛心的向老師和同學(xué)求教,爭取在師老師的指導(dǎo)下出色的完成畢業(yè)設(shè)計。第十六周: 進入畢業(yè)設(shè)計的后期工作,完善論文,準備答辯。擬出中期報告。第七周至第十二周: 初步完成具體的電路設(shè)計,運行通過。設(shè)計計劃:第一周至第二周:了解課題設(shè)計要求,查找書籍資料,安裝所需軟件。*對所設(shè)計系統(tǒng)有一個初步的設(shè)計方案。課題準備: *熟悉單片機及常用芯片的用法,查閱相關(guān)書籍資料。單片機負責(zé)從工業(yè)控制計算機上接收命令，并將其轉(zhuǎn)換成控制脈沖信號，從并行口發(fā)出到步進電機驅(qū)動電路。它的控制系統(tǒng)工作原理圖： 工業(yè)控制計算機是二維步進電機的控制系統(tǒng)的主機，負責(zé)從鍵盤接收外部命令由串行口輸出后，再經(jīng)接口電路發(fā)送單片機，然后接收單片機回送的命令數(shù)據(jù)并進行比較。此系統(tǒng)是工業(yè)控制計算機發(fā)出控制命令，通過與單片機的通信，按命令單片機產(chǎn)生控制步進電機運轉(zhuǎn)的脈沖信號。X5045 的片內(nèi)存儲器容量為 4K（或 512 字節(jié)） 。在這里，我將采用型號為 SN75LBC176，它的標準驅(qū)動節(jié)點數(shù)為 32，采用半雙工通訊。RS485 接口芯片已廣泛應(yīng)用于工業(yè)控制、儀器、儀表、多媒體網(wǎng)絡(luò)、機電一體化產(chǎn)品等眾多領(lǐng)域?；谝陨咸攸c，在需要 I/O 線不多的控制場合，選用它作為核心控制芯片，可使電路極大的簡化，而且程序的編寫及固化也相當方便、靈活。通過在單塊芯片上組合通用的 CPU 和 Flash 存儲器，使 AT89C51成為一強勁的微型計算機。ATMEL 公司把自身的先進 Flash 存儲器技術(shù)和 80C31 核相結(jié)合，生產(chǎn)出 Flash 單片機 AT89C51 系列。 *典型的 MCS51 系列單片機系統(tǒng)。 *本系統(tǒng)在工作、參數(shù)設(shè)定的兩種模式下實現(xiàn)三鍵輸入（復(fù)用） 。它允許將 2 根信號線或直流電源線在傳輸途中任意極性續(xù)接，容忍了布線施工的反接差錯，使工程施工大為方便。 本設(shè)計的中心即設(shè)計一個含有特定功能的典型單片機系統(tǒng)。本智能模擬負載，是針對自動化專業(yè)運動控制系統(tǒng)實驗中對負載對象及其變化規(guī)律要求而設(shè)計的。高頻電路宜采用多點串聯(lián)接地，地線應(yīng)短而粗。若線路板上既有邏輯電路又有線性電路，應(yīng)使它們盡量分開。這樣有利于排除銅箔與基板粘合劑受熱產(chǎn)生的揮發(fā)性氣體。此外，盡量避免使用大面積的銅箔，否則，長時間受熱時，容易發(fā)生銅箔膨脹和脫落現(xiàn)象。對于集成電路，其間距最小可到 。如有可能，接地線應(yīng)在 2～3mm 以上。尤其是電源線和地線。2 印制板導(dǎo)線的最小寬度主要由導(dǎo)線與絕緣基板間的粘附強度和流過它們的電流值決定。在整個布線過程中，應(yīng)遵循以下原則：1 輸入和輸出端的導(dǎo)線應(yīng)盡量避免相鄰平行。電路板的最佳形狀為矩形。布局過程中，應(yīng)盡量