【正文】 the dashed linedenotes the diagonal of the carrysave section. As the 4 least significant bits are discarded, the delay elements shown in the dotted squares need not be implemented. After the required number of multiplications and accumulations are made, the output should be clocked out and the accumulator reset. The structure of FIR filters facilitates their implementation using the pipelined MAC unit. The filter coefficients and the corresponding delayed inputs are fed to the multiplier in synchronized data streams, with their arrivals corresponding to the basic clock rate. An N tap filter requires N+1 clock cycles to plete the putation of one output.. FPGA ImplementationUnlike the unpipelined MAC unit, the routing delay is very critical in the pipelined MAC. This is because it takes ns for the output of the pipeline register to stabilize after it gets the clock, the output is then routed, and finally there is a ns delay in the next CLB Thus there is a minimum delay of ns and unless proper care is exercised, the routing delays may dominat。 these columns are represented in the layout by the small circles at the inputs to the adders. The numerous shifts encountered in the shift and add approach will very easily exhaust the routing resources. We have provided an empty column between every stage, which frees up additional routing resources. As shown in Figure 10, one second order section is placed on top of the other, for reasons discussed above, though the 24 columns available in the XC4013 might seem to satisfy the requirements for the two sections, which total only 23columns. The adders in this implementation use 22 bits, and the most significant 14 bits of the output of the dedicated carry adders are fed to the shift and add blocks.The sampling rate achieved with this configuration was morethan 10MHz.A number of other example fixedpoint filters were designed to evaluate the utility of this approach。 Computer EngineeringUniversity of KansasLawrence, KS 660452228ABSTRACTDigital filtering algorithms are most monly implemented using general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips and applicationspecific integrated circuits (ASICs) for higher rates. This paper describes an approach to the implementation of digital filter algorithms based on field programmable gate arrays (FPGAs).The advantages of the FPGA approach to digitalfilter implementation include higher sampling rates than are availablefrom traditional DSP chips,lower costs than an ASIC for moderate volume applications, and more flexibility than the alternate approaches.Since many current FPGA architectures are insystem programmable, the configuration of the device may be changed to implement differentfunctionality if required. Our examples illustrate that the FPGA approachis both flexible and provides performance parable or superior to traditional approaches.1. INTRODUCTIONThe most mon approaches to the implementation of digital filtering algorithms are general purpose digital signal processing chips for audio applications, or special purpose digital filtering chips andapplicationspecific integrated circuits (ASICs)for higher rates [9, 14]. This paper describes an approach to the implementation of digital filter algorithms on field programmable gate arrays (FPGAs).Recent advances in FPGA technology have enabled these devices to be applied to a variety of applications traditionally reserved for ASICs. FPGAs are well suited to datapath designs,such as those encountered in digital filteringapplications. The density of the new programmable devices is such that a nontrivial number of arithmetic operations such as those encountered in digital filtering may be implemented on a single device. The advantages of the FPGA approach to digital filter implementation include highersampling rates than are available from traditional DSP chips, lower costs than an ASIC for moderate volume applications, and more flexibility than the alternate particular, multiple multiplyaccumulate(MAC) units may be implemented on a single FPGA, which provides parable performance to generalpurpose architectures which have asingle MAC unit. Further, since many current FPGA architectures areinsystem programmable, the configuration of the device may be changed to implement alternate filtering operations, such as lattice filters andgradientbased adaptive filters, or entirely different functionality.2. BACKGROUNDResearch on digital filter implementation has concentrated on customimplementation using various VLSI technologies. The architecture ofthese filters has been largely determined by the target applications of the particular implementations. Several widely used digital signal processors such as the Texas Instruments TMS320,Motorola 56000, and Analog Devices ADSP2100 families have been designed to efficiently implement filtering operations at audio rates. These devices are extremely flexible, but are limited in performance. High performance designs for filtering at sampling rates above 100 MHz have also been demonstrated using CMOS[3, 4, 6, 8, 9, 14, 17, 19, 20, 21] and BiCMOS [8, 20, 22] technologies,using approaches ranging from full custom to traditionalfactoryconfigured gate arrays. These efforts have produced highperformance designs for specific application domains.There are several potential shortings of the custom VLSI approach, although it does promise the best performance and efficiency for the specific application for which a particular design is intended. The most obvious problem is the lack of flexibility in the custom approach. Custom devices are often suited only for use in a particular application, and can not be easily reconfigured for other operations even within that same domain. Another Problem which the customVLSI approach often imposes is a lack of adaptability once a device is in use within a sy