外文資料翻譯--基于c51兼容微處理器單片機(jī)的pwm控制器設(shè)計(jì)-單片機(jī)(參考版)
2025-05-17 04:38本頁面
【正文】 The PWM module also has the following features: ? Two PWM signal outputs with plementary or independent operation ? Hardware deadtime generators for plementary mode ? Duty cycle updates are configurable to be immediated or synchronized to the PWM Architecture of PWM Module Details of the architecture PMW generator The architecture of the 2output PWM generator shown in is based on a 16bit resolution counter which creates a pulsewidth modulated signal. The system is synthesized by a system clock signal whose frequency can be divided by 4 times or 12 times through setting the value of T3M for PWM0 or T4M for PWM1 in the special register PWMCON as shown in . To PWM0 generator, the clock to 16bit counter will be predivided by 4 times by default when T3M is set to zero. And the clock will be divided by 12 times when T3M is set to 1. This is also true for PWM1. The other bits in PWMCON are explained in detail in Table 1. Fig .4 Bit Mapping of PWMCON Table 1: The Bit Definition in PWMCON Channelselect logic The follow Fig. 5 shows the channelselect logic which is useful in Complementary Mode. From this diagram, it is clear to know that signal CP and CPWM control the source of PWMH and PWML. And the details about the two control signals will be discussed in the section 3, and the architecture of deadtime generator will also be discussed in section 5 for the continuity of Complementary Mode. Fig. 5 Diagram of Channelselect Logic Operation Mode and Simulation Results The design has two operation modes: Independent Mode and Complimentary Mode. By setting the corresponding bit CPWM in register PWMCON shown in user can select one of the two operation modes. When CPWM is set to zero, PWM module will work in Independent Mode, whereas, PWM module will work in Complimentary Mode. In the following of this section, the two operation mode will be explained respectively in detail and the simulation results of the PWM module from the Synoposys VCS EDA platform which verify the design will also be shown. Independent PWM Output Mode An Independent PWM Output mode is useful for driving loads such as the one shown in Figure 6. A particular PWM output is in the Independent Output mode when the corresponding CP bit in the PWMCON register is set to this case, twochannel PWM outputs are independent of each other. The signal on pin PWM0/PWMH is from PWM0 generator, and the signal on pin PWM1/PWML is from PWM0 generator. The sep
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