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【正文】 Timing Report Save As ? Timing Setup：讀入時序約束文件（ .sdc），設(shè)置時序信息，主要是Environment、 Optimization、 Parasitics、 Model四個比較常用的設(shè)置。 Placement Detach Scan Chains Setup Placement/ Timing Options AutoPlace Congestion OK Any setup, or many max tran/cap violations TNS WNS Pass Timing sanity check Any setup, or many max tran/cap violations From Floorplan Higheffort PPO Critical Range Opt To CTS Back to synthesis ? Placement：這一步是詳細的布局，一是要滿足設(shè)計的時序要求，二是保證后面的布線能夠順利進行。 CTS Setup Clock Common Options Clock Tree Synthesis Timing Setup Reconnect Scan Chains PostPlace Optimization Clock Tree Optimization Timing Report Save As Enable Propagated Clocks ? CTS：時鐘樹綜合，目的就是為了降低 clock skew，有很多 buffer構(gòu)成。 Route Std Cell PG routeVerify Setup Route Common Options Route Clock Nets Auto Route Global Route Route Optimization Track Assign Detail Route Search Repair Route Optimization Post Route CTO DRC Post Route Optimization Save As ? Route：布線，一般是先對電源線和時鐘信號線布線，然后再對信號線布線，目的就是為了最大滿足時序。 DFMData Out Fix Antenna Violations Set HPORoute Option Define Antenna File Report Antenna Ratio Search Repair Insert Diode Add Core Filler Slot Fat Wire Fill notch gap Fill Wire Track Run Final DRC LVS Hierarchical Verilog Out SPEF SDF File Out GDS File Out ? DFM：可制造性設(shè)計，
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