【正文】 erENI1I0SOUTPUT0XXX01I1XI0X1I1X1I1XI0X0I0XSOURCE INPUTAND GATES AS THE SWITCHESOUTPUTOR GATEENABLEDECODE OUTPUTSELECT INPUTDECODERSTANDARD MSI MULTIPLEXERS74X151: 8INPUT, 1BIT MULTIPLEXER(8選一)THE TRUTH TABLE:INPUTSOUTPUTSEN_LCBAYY_L1XXX010000D0D0’0001D1D1’0010D2D2’0011D3D3’0100D4D4’0101D5D5’0110D6D6’0111D7D7’74X157: 2INPUT, 4BIT MULTIPLEXER(4 2選一)THE TRUTH TABLE:INPUTSOUTPUTSG_LS1Y2Y3Y4Y1X0000001A2A3A4A011B2B3B4B74X153: 4INPUT, 2BIT MULTIPLEXER(2 4選一)THE TRUTH TABLE:INPUTSOUTPUTS 1G_L2G_LBA1Y2Y00001C02C000011C12C100101C22C200111C32C301001C0001011C1001101C2001111C30100002C0100102C1101002C2101102C311XX0074X251：8INPUT, 1BIT MULTIPLEXER WITH 3STATE OUTPUTTHE TRUTH TABLE:INPUTSOUTPUTSOE_LSELECTYY_LCBA1XXXHZHZ0000D0D0’0001D1D1’0010D2D2’0011D3D3’0100D4D4’0101D5D5’0110D6D6’0111D7D7’32/1 MULTIPLEXER USING 74X151EX: SHOW HOW TO BUILD THE FOLLOWING LOGIC FUNCTION USING 74X151.F=ΣABCD(2,4,6,14)F=A’B’CD’+A’BC’D’+A’BCD’+ABCD’ =(A’B’C+A’BC’+A’BC+ABC)D’ =D’ΣABC(1,2,3,7)MULTIPLEXER, DEMULTIPLEXER, AND BUSESEXCLUSIVEOR GATES AND PARITY CIRCUITXYX⊕Y(XOR)(X⊕Y)’(NXOR)0001011010101101FXOR=XY’+X’Y=X_L(Y_L)’+(X_L)’Y_L =(XY+X’Y’)’=(W_LY+WY_L)’|X=W_L PARITY CIRCUITSN XOR GATES MAY BE BUILD AN ODD PARITY CIRCUIT, BACAUSE ITS OUTPUT IS 1 IN AN ODD NUMBER OF ITS INPUTS ARE 1. IF THE OUTPUT OF THE ODDPARITY CIRCUIT IS INVERTED, WE GET AN EVENPARITY CIRCUIT,WHOSE OUTPUT IS 1 IF AN EVEN NUMBER OF ITS INPUT ARE 1.FIG 574 74X280 9BIT PARITY GENERATOR隨堂練習(xí)：1. FIND THE MINIMUM SUM OF PRODUCTS: F=ΣWXYZ(0,2,3,5,7,8,10,12,13) F=AD+AB+A’CD’+B’CD+A’BC’D F =ΣWXYZ(0,1,2,5,7,9)+D(6,8,11,13,14,15)2. Determine any static0 or static1 hazards in the follow equation. F=ΣABCD(5,7,8,9,10,11,13,15)習(xí)題：REPEAT DRILL (A),(B),(D), TRY USING 74X151, , , , , , parators a circuit that pares two binary words and indicates whether they are equal is called a parator. Some parators interpret their input words as signed or unsigned numbers and also indicate an arithmetic relationship ( greater or less than) between the words. These devices are often called magnitude parators.Comparator structure1 BIT COMPARATORThe logic function: DIFF=A0B0’+A0’B0The truth table and the circuit:A0B0DIFF0000111011104bit parator:ITERATIVE CIRCUITSAn iterative circuit is a special type of binational circuit, with the structure shown in figure579. The circuit contains n identical modules, each of which has both primary inputs and primary outputs and cascading inputs and outputs.A simple iterative algorithm:1. SET C0 TO ITS INITIAL VALUE AND SET i TO 02. Use Ci and PIi to determine the value of POi and Ci+13. Increment i4. If in, go to step 2The iterative structureAn iterative parator circuit1. set EQ0 to 1 and set i to 02. if EQi is 1 and Xi and Yi are equal, set EQi+1 to 1. else set EQi+1 to 0.3. increment i4. if in , go to step 2The iterative parator has less cost than the parallel parator shown in fig 578.STANDARD MSI COMPARATORThe 74x85 (fig 581) is a 4bit parator with a greaterthan, lessthan and equalto output, and has cascading inputs(greaterthan, lessthan and equalto).The logic functions:AGTBOUT=(AB)+(A=B)?AGTBINAEQBOUT=(A=B)?AEQBINALTBOUT=(AB)+(A=B)?ALTBINAND AB=A3?B3’+(A3⊕B3)’?A2?B2’+(A3⊕B3)’ ?(A2⊕B2)’?A1?B1’+(A3⊕B3)’ ?(A2⊕B2)’ ?(A1⊕B1)’?A0?B0’…..SEE PAGE ARITHMETIC CONDITIONS DERIVED FROM COMPARATOR’S OUTPUTSINPUT OUTPUTAGTBALTBAEQBAGEBATEBANEB010011100101001110ADDERS, SUBTRACTORSHALF ADDERS AND FULL ADDERSHALF ADDERSUM=X⊕Y=X?Y’+X’?YCO= X?YFULL ADDERSUM=X⊕Y⊕CIN =X?Y’?CIN’+X’?Y?CIN’+X’?Y’?CIN+X?Y?CINCOUT=X?Y+CIN?(X+Y)THE CIRCUIT SHOWN IN FIGURE 586RIPPLE ADDERSA ripple adder is a iterative circuit, shown in fig 587the maximun propagate delay Subtractors From the table 23D=X⊕Y⊕BINBOUT=X’?Y+BIN?(X’+Y) =X’?Y+BIN?X’+BIN?YBOUT’ =(X+Y’)?(X+BIN’)?(Y’+BIN’) =X?Y’+BIN’?(X+Y’)D= X⊕Y⊕BIN= X⊕Y’⊕BIN’COMPARE WITH THE FULL ADDER:SUM= X⊕Y⊕CINCOUT =X?Y+CIN?(X+Y)D= X⊕Y⊕BIN= X⊕Y’⊕BIN’BOUT’ =X?Y’+BIN’?(X+Y’)THE SUBTRACTOR IS SHOWN FIG 588CARRY LOKAHEAD ADDERSSi= Xi⊕Yi⊕CiCi+1 =Xi?Yi+Ci?(Xi+Yi)LET Gi = Xi?Yi Pi=Xi+YiSO Ci+1=Gi+Pi?CiC1=G0+P0?C0C2=G1+P1?C1=G1+P1?(G0+P0C0) =G1+P1?G0+P1?P0?C0C3=G2+P2?C2 =G2+P2?G1+P2?P1?G0+P2?P1?P0?C0C4=G3+P3?C3 =G3+P3?G2+P3?P2?G1+P3?P2?P1?G0+P3?P2?P1?P0?C0運(yùn)用：用加法器實現(xiàn)補(bǔ)碼的加減運(yùn)算。隨堂練習(xí)：1. FIND THE MINIMUM SUM OF PRODUCTS: F=ΣWXYZ(0,2,3,5,7,8,10,12,13) F=AD+AB+A’CD’+B’CD+A’BC’D F =ΣWXYZ(0,1,2,5,7,9)+D(6,8,11,13,14,15)2. Determine any static0 or static1 hazards in the follow equation. F=ΣABCD(5,7,8,9,10,11,13,15)習(xí)題：REPEAT DRILL (A),(B),(D), TRY USING 74X151, , , , , , , ,