【正文】 he gigabyte address point. Each VPB peripheral is allocated a 16 kilobyte address space within the VPB address connection of onchip peripherals to device pins is controlled by a Pin Connection Block. This must be configured by software to fit specific application requirements for the use of peripheral functions and pins.6. ARM7TDMIS PROCESSORThe ARM7TDMIS is a general purpose 32bit microprocessor, which offers high performance and very low power consumption.The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed Complex Instruction Set Computers. This simplicity results in a high instruction throughput and impressive realtime interrupt response from a small and costeffective techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically,while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from ARM7TDMIS processor also employs a unique architectural strategy known as THUMB, which makes it ideally suited to highvolume applications with memory restrictions, or applications where code density is an issue.The key idea behind THUMB is that of a superreduced instruction set. Essentially, the ARM7TDMIS processor has two instruction sets:? The standard 32bit ARM instruction set.? A 16bit THUMB instruction set.The THUMB set’s 16bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16bit processor using 16bit registers. This is possible because THUMB code operates on the same 32bit register set as ARM code. THUMB code is able to provide up to 65% of the code size of ARM, and 160% of the performance of an equivalent ARM processor connected to a 16bit memory system. The ARM7TDMIS processor is described in detail in the ARM7TDMIS Datasheet that can be found on。7. ONCHIP FLASH MEMORY SYSTEMThe LPC2114/2212 incorporate a 128 kB Flash memory system, while LPC2124/2214 incorporate a 256 kB Flash memory system. This memory may be used for both code and data storage. Programming of the Flash memory may be acplished in several ways: over the serial builtin JTAG interface, using In System Programming (ISP) and UART0, or by means of In Application Programming (IAP) capabilities. The application program, using the In Application Programming (IAP) functions, may also erase and/or program the Flash while the application is running, allowing a great degree of flexibility for data storage field firmware upgrades, etc.8. ONCHIP STATIC RAMThe LPC2114/2124/2212/2214 provide a 16 kB static RAM memory that may be used for code and/or data storage. The SRAMsupports 8bit, 16bit, and 32bit accesses.The SRAM controller incorporates a writeback buffer in order to prevent CPU stalls during backtoback writes. The writeback buffer always holds the last data sent by software to the SRAM. This data is only written to the SRAM when another write is requested by software (the data is only written to the SRAM when software does another write). If a chip reset occurs, actual SRAM contents will not reflect the most recent write request (. after a warm chip reset, the SRAM does not reflect the last write operation). Any software that checks SRAM contents after reset must take this into account. Two identical writes to a location guarantee that the data will be present after a Reset. Alternatively, a dummy write operation before entering idle or powerdown mode will similarly guarantee that the last data written will be present in SRAM after a subsequen Reset.9. LPC2114/2124/2212/2214 REGISTERSAccesses to registers in LPC2114/2124/2212/2214 is restricted in the following ways:1) user must NOT attempt to access any register locations not defined.2) Access to any defined register locations must be strictly for the functions for the registers.3) Register bits labeled ’’, ’0’ or ’1’ can ONLY be written and read as follows: ’’ MUST be written with ’0’, but can return any value when read (even if it was written with ’0’). It is a reserved bit and maybe used in future derivatives. ’0’ MUST be written with ’0’, and will return a ’0’ when read. ’1’ MUST be written with ’1’, and will return a ’1’ when read.10. PULSE WIDTH MODULATOR (PWM)LPC2114/2124/2212/2214 Pulse Width Modulator is based on standard Timer 0/1 described in previous chapter. Application can choose among PWM and match functions available .FEATURES? Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types.The match registers also allow: Continuous operation with optional interrupt generation on match. Stop timer on match with optional interrupt generation. Reset timer on match with optional interrupt generation.Figure 1: LPC2114/2124/2212/2214 Block Diagram? An external output for each match register with the following capabilities: Set low on match. Set high on match. Toggle on match. Do nothing on match.? Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses.? Pulse period and width can be any number of timer counts. This allows plete flexibility in the tradeoff between resolution and repetition rate. All PWM outputs will occur at the same repetition rate.? Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses.? Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Sof