【正文】 ecific Integrated Circuit An applicationspecific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for generalpurpose use. For example, a chip designed solely to run a cell phone is an ASIC. In contrast, the 7400 series and 4000 series integrated circuits are logic building blocks that can be wired together for use in many different applications. As feature sizes have shrunk and design tools improved over the years, the maximum plexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 ASICs often include entire 32bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (SystemonChip). Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs. Fieldprogrammable gate arrays (FPGA) are the modern day equivalent of 7400 series logic and a breadboard, containing programmable logic blocks and programmable interconnects that allow the same FPGA to be used in many different applications. For smaller designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC design. The nonrecurring engineering cost (the cost to setup the factory to produce a particular ASIC) can run into hundreds of thousands of dollars. The general term application specific integrated circuit includes FPGAs, but most designers use ASIC only for nonfield programmable devices and make a distinction between ASIC and FPGAs.HistoryThe initial ASICs used gate array technology. Ferranti produced perhaps the first gatearray, the ULA (Unmitted Logic Array), around 1980. Customization occurred by varying the metal interconnect mask. ULAs had plexities of up to a few thousand gates. Later versions became more generalized, with different base dies customized by both metal and polysilicon layers. Some base dies include RAM elements.Standard cell designIn the mid 1980s a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third party design tools were available, there was not an effective link from the third party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC designers ended up using factory specific tools to plete the implementation of their designs. A solution to this problem that also yielded a much higher density device was the implementation of Standard Cells. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance。 that could also be represented in third party cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (NonRecurring Engineering) and recurring ponent cost.By the late 1980s, logic synthesis tools, such as Design Compiler, became available. Such tools could pile HDL descriptions into a gatelevel netlist. This enabled a style of design called standardcell design. Standardcell Integrated Circuits (ICs) are designed in the following conceptual stages, although these stages overlap significantly in practice.These steps, implemented with a level of skill mon in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.A team of design engineers starts with a nonformal understanding of the required functions for a new ASIC, usually derived from requirements analysis.*The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a puter program in a highlevel language. This is usually called the RTL (register transfer level) design. *Suitability for purpose is verified by simulation. A virtual system created in software, using a tool such as Virtutech’s Simics, can simulate the performance of ASICs at speeds up to billions of simulated instructions per second. *A logic synthesis tool, such as Design Compiler, transforms the RTL design into a large collection of lowerlevel constructs called standard cells. These constructs are taken from a standardcell library consisting of precharacterized collections of gates such as 2 input nor, 2 input nand, inverters, standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gatelevel netlist. *The gatelevel netlist is next processed by a placement tool which places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints. Sometimes advanced techniques such as simulated annealing are used to optimize placement. *The routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them. Since the search space is large, this process will produce a “sufficient” rather than “globallyoptimal” solution. The output is a set of photomasks enabling semiconductor fabrication to produce physical ICs. *Close estimates of final delays, parasitic resistances and capacitances, and power consumptions can then be made. In the case of a digital circuit, this will be further mapped into delay information. These estimates are used in a final round of testing. This testing demonstrates that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is plete the photomask information is released for chip fabrication. These design steps (or flow) are also mon to standard product des