【正文】 test, the lowest development cost and risk one of the smallest devices. 5) FPGA CHMOS process highspeed, low power consumption with CMOS, TTLlevel patible. It can be said, FPGA chips are lowvolume system to improve system integration, reliability, one of the best. FPGA is stored in the onchip RAM, the procedure to set the status of their work, so work needs to be programmed onchip RAM. Users can configure the different modes, different style of programming. When power, FPGA chip will read the data in EPROM chip program RAM, the configuration is plete, FPGA into working condition. After powerdown, FPGA recovery as white film, the internal logic disappear, so, FPGA can be used repeatedly. FPGA programming without a dedicated FPGA programmer, just use mon EPROM, PROM programmer can be. When the need to modify the FPGA functionality, just for an EPROM can be. In this way, with an FPGA, different programming data, can produce different circuit functions. Therefore, FPGA39。s use of very flexible. FPGA configuration mode A variety of FPGA configuration modes: Master mode is a parallel FPGA plus an EPROM way。 masterslave mode can support a multichip PROM programming FPGA。 serial mode can be programmed using the serial PROM FPGA。 peripheral model can be used as microFPGA processor, peripherals, from the microprocessor to its programming. How to achieve rapid timing closure and lower power consumption and costs, optimize and reduce the FPGA clock management in parallel with the PCB design plexity and other issues, has been the use of FPGA system designers need to consider the key issues. Now, with the FPGA to a higher density, higher capacity, lower power consumption, and integrate more in the direction of IP, system design engineers to benefit from these excellent performance at the same time, had to face the unprecedented performance and FPGA ability to bring a new level of design challenges. For example, the leading FPGA vendors Xilinx recently announced Virtex5 family uses 65nm technology, can provide up to 330,000 logic cells, 1,200 I / O and a lot of hard IP blocks. Large capacity and density of the plex wiring bees more unpredictable, and the resulting more serious problem of timing closure. In addition, integration of different applications, a greater number of logic functions, DSP, embedded processing and interface modules, and let the clock management and voltage distribution more difficult. Fortunately, FPGA vendors, EDA tool vendors are working together to solve unique design challenges of 65nm FPGA. Not long ago, Synplicity and Xilinx announced the formation of largecapacity timing closure joint working group designed to help maximize system design engineers a faster and more efficient way to apply 65nm FPGA devices. Design software supplier Magma Blast FPGA synthesis tool launched to help create an optimized layout, speeding up the convergence of timing. FPGA major manufacturers 1. Altera 2. Xilinx 3. Actel 4. Lattice Altera and Xilinx which mainly produce generalpurpose FPGA, its main products using RAM technology. Actel mainly provide nonvolatile FPGA, antifusebased technology products and FLASH technology. Notes on FPGA design Whether you are a logic designers, hardware engineers or system engineers, or even have all of these titles, as long as you39。re in any kind of highspeed and multiprotocol used in plex systems FPGA, you likely need to resolve device configuration, power management, IP integration, signal integrity, and other key design issues. However, you do not have to face these challenges alone, because in the current industryleading FPGA pany39。s application engineers work every day to face these problems, and they have made some design work will make you bee more relaxed design guidelines and solutions. I / O signal allocation Can provide the most versatile pin, I / O standards, programs and differential termination in signal distribution on the FPGA also has the most plex design guidelines. Although Altera FPGA device design guidelines do not (because it is easier to implement), but the Xilinx FPGA design guidelines is very plex. But no matter what kind of situation for the I / O pin assignment signal, there are some mon steps to keep in mind: a spreadsheet listing all of the signal distribution scheme, and their important properties, such as I / O standard, voltage, required termination method and the associated clock. the manufacturer39。s block / regional patibility guidelines. using a second formulation of the spreadsheet layout of FPGA to determine which pins are mon, which is dedicated, which support differential signals and the global and local clock, which required reference voltage. using the above two areas of information and patibility criteria, the first distribution of the maximum signal level restricted to the pin, the final distribution by the least restrictive. For example, you may need to assign the serial bus and clock signals, because they are usually assigned to specific pins. accordance with the degree of redistribution of the restricted signal bus. At this stage, you may need to carefully weigh the simultaneous switching output (SSO) and is not patible I / O standards and other design issues, especially when you have a lot of highspeed output, or use several different I / O standards. If your design requires local / regional clock, you will probably need to use highspeed bus near the pin, it is best to remember this requirement in advance, so that the final arrangements can not be the most suitable for their pin. If a particular block of the selected I / O standards requires reference voltage signal, remember to do the distribution of these pins. The distribution of the differential signal is always first on the singleended signals. If a FPGA chip termination provided, it may also apply to other patibility rules. 6. Where appropriate allocation of the remaining signal. At t