基于fpgacpld的通用異步通信接口uart建模與設計-資料下載頁
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【正文】 A的UART設計．現(xiàn)代電子技術. 2006，(2)127129．[6] 鄒杰, 楊建寧．基于FPGA的UART控制器的設計和實現(xiàn). 微計算機信息．[7] 潘松, 黃繼業(yè)．EDA技術實用教程 [M] . 北京：科學出版社，2002，10．[8] 林容益． CPU/SOC及外圍電路應用設計(基于FPGA/CPLD) ．北京：北京航空航天大學出版社，2004.[9] programmable munication interface datasheet．[A]．7altera．．．2004/2005．9The Design of UART(Universal Asynchronous Receiver Transmitter)based onFPGA/CPLD【Abstract】FPGA/CPLD is the product of LSL(large Scale Integration), it is the attribute of semicustom Integrate Circuit, bining EDA with FPGA/CPLD will construct the digital system quickly and expediently. FPGA is the electron to design a technology with vigor and development prospect in the field, in influence last the seventies the 20th century at all the onechip puter one invention and use. Can say overstating at all, FPGA can finish the function of any digital device. As EDA software and hardware describe the progress of the language (HDL), the development period of FPGA is shorter and shorter, the products function are stronger and stronger. FPGA handles the more and more important role of the performer in the field in the plicated logical circuit and digital signal.UART(Universal Asynchronous Receiver Transmitter) is a short haul serial munication interface which is applied widely in digital munication. This design has used the multimodular realization method, introduces Verilog the DHL hardware description language to develop the design of UART(Universal Asynchronous Receiver Transmitter) based on FPGA/CPLD. The structure of the system is divided in modularization so that can fit the method TopDown. The hardcore of this system is implemented with finite state machine(FSM), it makes the logic of control more intuitionistic and more briefness. The efficiency of the design is improved in a wide range. The implementation of design, simulation and synthesis were pleted by the development software of and .【Key Words】FPGA/CPLD；UART； Multimodels 。Finite State Machine
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