【正文】 amplifier. The internal reference may be routed via the VREF pin to external system ponents or to the voltage reference input pins shown in Figure . Bypass capacitors of μF and μF are remended from the VREF pin to AGND, as shown in Figure . See Table for voltage reference specifications.The Reference Control Register, REF0CN (defined in Figure ) enables/disables the internal reference generator and selects the reference inputs for ADC0 and ADC1. The BIASE bit in REF0CN enables the onboard reference generator while the REFBE bit enables the gainoftwo buffer amplifier which drives the VREF pin. When disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 μA (typical) and the output of the buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator, BIASE and REFBE must both be set to logic 1. If the internal reference is not used, REFBE may be set to logic 0. Note that the BIASE bit must be set to logic 1 if either DAC or ADC is used, regardless of whether the voltage reference is derived from the onchip reference or supplied by an offchip source. If neither the ADC nor the DAC are being used, both of these bits can be set to logic 0 to conserve power. Bits AD0VRS and AD1VRS select the ADC0 and ADC1 voltage reference sources, respectively. The electrical specifications for the Voltage Reference circuit are given in Table .The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see Section “. Analog Multiplexer and PGA” on page 43 for C8051F020/1 devices, or Section “. Analog Multiplexer and PGA” on page 59 for C8051F022/3 devices). The TEMPE bit within REF0CN enables and disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any A/D measurements performed on the sensor while disabled result in undefined data.VOLTAGE REFERENCE (C8051F021/3) The internal voltage reference circuit consists of a V, 15 ppm/176。C (typical) bandgap voltage reference generator and a gainoftwo output buffer amplifier. The internal reference may be routed via the VREF pin to external system ponents or to the VREFA input pin shown in Figure . Bypass capacitors of μF and μF are remended from the VREF pin to AGND, as shown in Figure . See Table for voltage reference specifications.The VREFA pin provides a voltage reference input for ADC0 and ADC1. ADC0 may also reference the DAC0 output internally, and ADC1 may reference the analog power supply voltage, via the VREF multiplexers shown in Figure .The Reference Control Register, REF0CN (defined in Figure ) enables/disables the internal reference generator and selects the reference inputs for ADC0 and ADC1. The BIASE bit in REF0CN enables the onboard reference generator while the REFBE bit enables the gainoftwo buffer amplifier which drives the VREF pin. When disabled, the supply current drawn by the bandgap and buffer amplifier falls to less than 1 μA (typical) and the output of the buffer amplifier enters a high impedance state. If the internal bandgap is used as the reference voltage generator, BIASE and REFBE must both be set to 1 (this includes any time a DAC is used). If the internal reference is not used, REFBE may be set to logic 0. Note that the BIASE bit must be set to logic 1 if either ADC is used, regardless of whether the voltage reference is derived from the onchip reference or supplied by an offchip source. If neither the ADC nor the DAC are being used, both of these bits can be set to logic 0 to conserve power. Bits AD0VRS and AD1VRS select the ADC0 and ADC1 voltage reference sources, respectively. The electrical specifications for the Voltage Reference are given in Table The temperature sensor connects to the highest order input of the ADC0 input multiplexer (see Section “. Analog Multiplexer and PGA” on page 43 for C8051F020/1 devices, or Section “. Analog Multiplexer and PGA” on page 59 for C8051F022/3 devices). The TEMPE bit within REF0CN enables and disables the temperature sensor. While disabled, the temperature sensor defaults to a high impedance state and any A/D measurements performed on the sensor while disabled result in undefined data.附錄C：外文資料翻譯譯文部分C8051F020 12 位電壓輸出DAC每個(gè)C8051F020/1/2/3 器件都有兩個(gè)片內(nèi)12 位電壓方式數(shù)/模轉(zhuǎn)換器（DAC）。每個(gè)DAC的輸出擺幅均為0V 到（VREF1LSB），對(duì)應(yīng)的輸入碼范圍是0x000 到0xFFF?？梢杂脤?duì)應(yīng)的控制寄存器DAC0CN 和DAC1CN 使能/禁止DAC0 和DAC1。在被禁止時(shí)，DAC 的輸出保持在高阻狀態(tài)，DAC 的供電電流降到1μA 或更小。每個(gè)DAC 的電壓基準(zhǔn)在VREFD（C8051F020/2）或VREF（C8051F021/3）引腳提供。注意：C8051F021/3 的VREF 引腳可以由內(nèi)部電壓基準(zhǔn)或一個(gè)外部源驅(qū)動(dòng)。如果使用內(nèi)部電壓基準(zhǔn)，為了使DAC 輸出有效，該基準(zhǔn)必須被使能。有關(guān)配置DAC 電壓基準(zhǔn)的詳細(xì)信息，見“9. 電壓基準(zhǔn)（C8051F020/2）”或“（C8051F021/3）”。1. DAC 輸出更新每個(gè) DAC 都具有靈活的輸出更新機(jī)制，允許無縫的滿度變化并支持無抖動(dòng)輸出更新，適合于波形發(fā)生器應(yīng)用。下面的描述都是以DAC0 為例，DAC1 的操作與DAC0 完全相同。注意：讀DAC0L 返回預(yù)鎖存數(shù)據(jù)，所讀值是最后寫入到該寄存器的數(shù)據(jù)，而不是DAC0L 鎖存器中的值。 根據(jù)軟件命令更新輸出在缺省方式下（DAC0CN.[4:3] =‘00’），DAC0 的輸出在寫DAC0 數(shù)據(jù)寄存器高字節(jié)（DAC0H）時(shí)更新。注意：寫DAC0L 時(shí)數(shù)據(jù)被保持，對(duì)DAC0 輸出沒有影響，直到對(duì)DAC0H的寫操作發(fā)生。如果向DAC 數(shù)據(jù)寄存器寫入一個(gè)12 位字，則12 位的數(shù)據(jù)字被寫到低字節(jié)（DAC0L）和高字節(jié)（DAC0H）數(shù)據(jù)寄存器。在寫DAC0H 寄存器后數(shù)據(jù)被鎖存到DAC0。因此，如果需要12 位分辨率，應(yīng)在寫入DAC0L 之后寫DAC0H。DAC 可被用于8 位方式，這種情況是將DAC0L 初始化一個(gè)所希望的數(shù)值（通常為0x00），將數(shù)據(jù)只寫入DAC0H（有關(guān)在16 位SFR 空間內(nèi)對(duì)12 位DAC 節(jié)）。 基于定時(shí)器溢出的輸出更新在ADC 轉(zhuǎn)換操作中，ADC 轉(zhuǎn)換可以由定時(shí)器溢出啟動(dòng)，不用處理器干預(yù)。與之類似，DAC 的輸出更新也可以用定時(shí)器溢出事件觸發(fā)。這一特點(diǎn)在用DAC 產(chǎn)生一個(gè)固定采樣頻率的波形時(shí)尤其有用，可以消除中斷響應(yīng)時(shí)間不同和指令執(zhí)行時(shí)間不同對(duì)DAC 輸出時(shí)序的影響。當(dāng)DAC0MD 位（DAC0CN.[4:3]）被設(shè)置為‘01’、‘10’或‘11’時(shí)，對(duì)DAC 數(shù)據(jù)寄存器的寫操作被保持，直到相應(yīng)的定時(shí)器溢出事件（分別為定時(shí)器定時(shí)器4 或定時(shí)器2）發(fā)生時(shí)DAC0H:DAC0L 的內(nèi)容才被復(fù)制到DAC 輸入鎖存器，允許DAC 數(shù)據(jù)改變?yōu)樾轮怠? DAC 輸出定標(biāo)/調(diào)整在某些情況下，對(duì)DAC0 進(jìn)行寫入操作之前應(yīng)對(duì)輸入數(shù)據(jù)移位，以正確調(diào)整DAC 輸入寄存器中的數(shù)據(jù)。這種操作一般需要一個(gè)或多個(gè)裝入和移位指令，因而增加軟件開銷和降低DAC的數(shù)據(jù)通過率。為了減少這方面的負(fù)擔(dān)，數(shù)據(jù)格式化功能為用戶提供了一種能對(duì)數(shù)據(jù)寄存器DAC0H 和DAC0L 中的數(shù)據(jù)格式編程的手段。三個(gè)DAC0DF 位（DAC0CN.[2:0]）允許用戶在5 種數(shù)據(jù)字格式指定一種，見DAC0CN 寄存器定義。DAC1 的功能與上述DAC0 的功能完全相同。 給出了DAC0 和DAC1 的電氣特性。電壓基準(zhǔn)（C8051F020/2）電壓基準(zhǔn)電路為控制ADC 和DAC 模塊工作提供了靈活性。有三個(gè)電壓基準(zhǔn)輸入引腳，允許每個(gè)ADC 和兩個(gè)DAC 使用外部電壓基準(zhǔn)或片內(nèi)電壓基準(zhǔn)輸出。通過配置VREF 模擬開關(guān)，ADC0 還可以使用DAC0 的輸出作為內(nèi)部基準(zhǔn)，ADC1 可以使用模擬電源電壓作為基準(zhǔn)。、15ppm/℃（典型值）的帶隙電壓基準(zhǔn)發(fā)生器和一個(gè)兩倍增益的輸出緩沖放大器組成。內(nèi)部基準(zhǔn)電壓可以通過VREF 所示的電壓基準(zhǔn)輸入引腳。建議在VREF 引腳與AGND μF μF 的旁路電容， 所示?；鶞?zhǔn)電壓控制寄存器REF0CN（）使能/禁止內(nèi)部