【正文】 the multicores chip are discussed, and proposed a Physical Layer Control scheme on GSM baseband chip, and designed a based clock unit according the frame structure of GSM, and established the physical layer scheduling sequence, initially pleted the scheduling and controlling of multicores on SOC.Key Words: GSM；Physical Layer Controller；SoC；scheduling0 引言 Current mobile phones as baseband processor core, its main function such as implementing protocol processing, human interface and simple applications and so on. GSM is the world39。s most widely used wireless, because the most largest group of user and network investment,in the future,GSM will be existing long time .there are many options realize baseband chip,nowadays the most of baseband chip are made of multi_core integrated design framework,from the system structure dipartition point of view,the baseband processor can be divided into the following subsystems: CPU subsystem, voice codec subsystem DSP channel codec subsystem and peripherals onchip bus subsystems, CPU subsystem generally plete the entire mobile station control and management, including timing control, digital control system, radio control, humanmachine interface control. Thus ,it’s essential for software use in the physical layer control, For the different system architectures and different physical layer protocols. The control programs have different with capability. So therefore ,the it’s very important for the physical layer control research.1 Design basis Universal chip architecture Used in this article is a generic architecture baseband chip[1] , shown in Figure 1, the upper and lower rows were used a DSP, to plete the physical layer signal processing, due to the plexity of the task and the algorithm downlink higher than upstream, extra piece of hardware coprocessors, CPU subsystem using a piece of opensource RISC processors, protocol stack software running on a ARM7 processor, between the physical layer and protocol stack with a dualport SRAM connection.BCCoprocessorRF excuse Figure 1 Figure baseband chip architecture Physical layer frame structure GSM system adopt the FDD mode ,the frame structure is as follows: a TDMA frame as a unit, one multiframe (multiframe is divided into 26 and 52 multiframe) is equal to 26 or 52 multiframes, a superframe is equal to 1326 TDMA frame, an ultra frame is equivalent to 2048 superframe (2,715,648 TDMA frames), and each TDMA frame is divided into eight time slots, each slot duration milliseconds and a bit time slot is equal to . For control physical layer signal processing, the base clocks are provided to the frame number ,and the slot number to achieve every parts synchronous execution. Baseband data current Following a full rate speech channel as example[2] , tasking into the baseband data processing and task shine upon a specific in the picture 2. Figure 2 voice channel process 2 Control Strategy Static and dynamic schedulingControl scheme for physical layer task scheduling like realtime operating system task scheduling ,which can be classify static and dynamic dynamic task scheduling depend on the priority tasks that dynamically allocated,you can use the preemptive and goal of static scheduling is assigning tasks to each hardware processor,and each processor giving the static timing what the tasks running need,it’s very simple for the scheduling algorithm,and the less mobile munication processing sequence baseband chip is based on the physical layer protocol, timing controllable and less outbreak,which can speeding less time to finish the timing allocation and task mapping,therefore,this task adopted static task scheduling,it will task mapped directly to a particular processor unit and divided the the storage space resources,there is no parallelism task trying best to map on the same processor unit. Centralized control and masterslave controlPhysical layer control module controls the physical layer module depend on the task state transitions,According to the system each processing unit in the number of tasks, plexity, and processing delay as a consideration, to determine the use of centralized control or masterslave control. the masterslave control scheme,the main control system is responsible for the entire baseband processor chip management,including receiving highlevel mands, running internal control with logic processing, transmission control mands to the auxiliary control system。Slave control systems mandate a single processor of the control unit ,includes a mand receiving host system ,reads the configuration parameters, associated with logical puting, called subtasks performing the the main control system and auxiliary control systems, and auxiliary control systems and auxiliary control system interfaces to interact through the task, the task interface includes a software interface and hardware interfaces, software interfaces refers to the data message interface, hardware interface refers to the signal port.Centralized control, all control task throughout the entire baseband to RISC processor (equivalent to an operating system),DSP no longer maintain their own separate task queue, and no longer has the task of interactive interfaces between multiple DSP, only retain data transmission,RISC for all peripheral interrupt prioritization and response, considering the control scheme described in this article centralized control, thereby greatly reducing the consumption of various DSP processors.8. control schemeMost of the time the mobile terminal is in IDLE mode, and may be in a discontinuous reception (DRX) state, only required to a broadcast channel and a specific paging group PCH for monitoring ,So can be shut off in specific time frame system of the high speed clock, reduce the power consumption of the system. base clock designSOC chip described in this