【文章內容簡介】 s ga s e s c o m m o n i n dr y e t c h pr o c e s s .169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda Disadvantages of CMP Table D is advant age s R e m a r k s1. N e w t e c hn o l o g y CM P i s a n e w t e c hn o l o gy fo r w a f e r p l a na r i z a t i o n. T h e r e i s r e l a t i v e l ypo o r c o n t r o l o v e r t h e p r o c e s s v a r i a b l e s w i t h a n a rr o w pr o c e s s l a t i t ude .2. N e w de fe c t s N e w t y p e s of de f e c t s f r o m CM P c a n a f fe c t di e y i e l d. T h e s e de f e c t sb e c o m e m o r e c r i t i c a l f o r s ub 0. 25 ? m f e a t u r e s i z e s .3. N e e d fo r a d di t i o na lpr o c e s s de v e l o pm e n tCM P r e qui r e s a ddi t i o na l p r o c e s s de v e l o pm e n t f o r p r o c e s s c o n t r o l a n dm e t r o l o g y . A n e xa m pl e i s t h e e n d po i nt o f CM P i s di f f i c ul t t o c o n t r o lfo r a de s i r e d t h i c k n e s s .4. Co s t of ow n e r s h i p i shi g hCM P i s e xpe n s i v e t o o pe r a t e b e c a us e o f c o s t l y e qui pm e n t a n dc o n s um a b l e s . CM P p r o c e s s m a t e ri a l s r e qu i r e h i g h m a i n t e na n c e a n df r e que n t r e pl a c e m e n t o f c h e m i c a l s a nd p a r t s .169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda CMP Oxide Mechanism Figure SiO2 layer Polishing pad Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si CMP System (5) Byproduct removal (1) Slurry dispense Byproducts (2) H2O OH travel to wafer surface (4) Surface reactions and mechanical abrasion Drain Slurry (3) Mechanical force presses slurry into wafer Si(OH)4 Rotation Si 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda Mechanism for Metal CMP Figure Polishing pad 2) Mechanical abrasion Rotation 1) Surface etch and passivation 3) Repassivation Slurry Downforce Oxide Metal Oxide Metal Oxide Metal 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda CMP Erosion in High Wiring Density Tungsten interconnect (soft material, high polish rate) Erosion Oxide (hard material, low polish rate) Figure 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda Inplete Via Etch due to Erosion SiO2 Via etch is inplete due to nonuniform SiO2 thickness variation caused by erosion in preceding dielectric layer Aluminum Tungsten via LI tungsten Tungsten via Unplanarized SiO2 Planarized SiO2 Planarized SiO2 First incidence of erosion Figure 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda CMP Dishing in a Large Feature Nitride polish stop Dishing Oxide (hard surface, low polish rate) Copper removal Copper (soft surface, high polish rate) Figure 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda CMP Polishing Pad Porous surface Figure 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian Serda CMP Polishing Pad Photo courtesy of SpeedfamIPEC Photo 169。 2023 by Prentice Hall Semiconductor Manufacturing Technology by Michael Quirk and Julian S