【文章內(nèi)容簡(jiǎn)介】 如分支，電路，陷阱和中斷。這些地址，可以從主機(jī)端的調(diào)試軟件，可以由指令執(zhí)行跟蹤進(jìn)行重建指定的精確。此外，執(zhí)行跟蹤數(shù)據(jù)以壓縮格式被存儲(chǔ)，使得一個(gè)幀代表以上的一個(gè)指令。如這些優(yōu)化的結(jié)果，實(shí)際開始和結(jié)束點(diǎn)跟蹤收集在執(zhí)行過(guò)程中可能會(huì)從用戶指定的啟動(dòng)和結(jié)束略有不同。數(shù)據(jù)跟蹤存儲(chǔ)要求100％跟蹤緩沖區(qū)實(shí)時(shí)加載和存儲(chǔ)。當(dāng)存儲(chǔ)到跟蹤緩沖區(qū)，數(shù)據(jù)跟蹤幀的優(yōu)先級(jí)低于執(zhí)行跟蹤框架。因此，當(dāng)數(shù)據(jù)幀在實(shí)時(shí)存儲(chǔ)時(shí)，執(zhí)行和跟蹤數(shù)據(jù)都不能保證正好與每個(gè)同步等。附件2：外文原文（復(fù)印件）2. Processor ArchitectureThis chapter describes the hardware structure of the Nios174。II processor, including a discussion of all the functional units of the Nios II architecture and the fundamentals of the Nios II processor hardware implementation. This chapter contains the following sections:■ “Processor Implementation” on page 2–2■ “Register File” on page 2–3■ “Arithmetic Logic Unit” on page 2–4■ “Reset and Debug Signals” on page 2–8■ “Exception and Interrupt Controllers” on page 2–8■ “Memory and I/O Organization” on page 2–10■ “JTAG Debug Module” on page 2–17The Nios II architecture describes an instruction set architecture (ISA). The ISA in turn necessitates a set of functional units that implement the instructions. A Nios II processor core is a hardware design that implements the Nios II instruction set and supports the functional units described in this document. The processor core does not include peripherals or the connection logic to the outside world. It includes only the circuits required to implement the Nios II architecture.The Nios II architecture defines the following functional units:■ Register file■ Arithmetic logic unit (ALU)■ Interface to custom instruction logic■ Exception controller■ Internal or external interrupt controller■ Instruction bus ■ Data bus ■ Memory management unit (MMU)■ Memory protection unit (MPU)■ Instruction and data cache memories■ Tightlycoupled memory interfaces for instructions and data■ JTAG debug moduleProcessor ImplementationThe functional units of the Nios II architecture form the foundation for the Nios II instruction set. However, this does not indicate that any unit is implemented in hardware. The Nios II architecture describes an instruction set, not a particular hardware implementation. A functional unit can be implemented in hardware, emulated in software, or omitted entirely. A Nios II implementation is a set of design choices embodied by a particular Nios II processor core. All implementations support the instruction set defined in the Instruction Set Reference chapter of the Nios II Processor Reference Handbook. Each implementation achieves specific objectives, such as smaller core size or higher performance. This flexibility allows the Nios II architecture to adapt to different target applications. Implementation variables generally fit one of three tradeoff patterns: more or less of a feature。 inclusion or exclusion of a feature。 hardware implementation or software emulation of a feature. An example of each tradeoff follows: ■ More or less of a feature—For example, to finetune performance, you can increase or decrease the amount of instruction cache memory. A larger cache increases execution speed of large programs, while a smaller cache conserves onchip memory resources.■ Inclusion or exclusion of a feature—For example, to reduce cost, you can choose to omit the JTAG debug module. This decision conserves onchip logic and memory resources, but it eliminates the ability to use a software debugger to debug applications.■ Hardware implementation or software emulation—For example, in control applications that rarely perform plex arithmetic, you can choose for the division instruction to be emulated in software. Removing the divide hardware conserves onchip resources but increases the execution time of division operations. For information about which Nios II cores supports what features, refer to the Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook. For plete details about userselectable parameters for the Nios II processor, refer to the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook.Register FileThe Nios II architecture supports a flat register file, consisting of thirtytwo 32bit generalpurpose integer registers, and up to thirtytwo 32bit control registers. The architecture supports supervisor and user modes that allow system code to protect the control registers from errant applications.The Nios II processor can optionally have one or more shadow register sets. A shadow register set is a plete set of Nios II generalpurpose registers. When shadow register sets are implemented, the CRS field of the status register indicates which register set is currently in use. An instruction access to a generalpurpose register uses whichever register set is active.A typical use of shadow register sets is to accelerate context switching. When shadow register sets are implemented, the Nios II processor has two special instructions, rdprs and wrprs, for moving data between register sets. Shadow register sets are typically manipulated by an operating system kernel, and are transparent to application code. A Nios II processor can have up to 63 shadow register sets.For details about shadow register set implementation and usage, refer to “Registers” and “Exception Processing” in the Programming Model chapter of the Nios II Processor Reference Handbook. For details about the rdprs and wrprs instructions, refer to the Instruction Set Reference chapter of the Nios II Processor Reference Handbook. The Nios II architecture allows for the future addition of floatingpoint registers. Arithmetic Logic UnitThe Nios II ALU operates on data stored in generalpurpose registers. ALU operations take one or two inputs from registers, and store a result back in a register.Unimplemented InstructionsSome Nios II processor core implementations do not provide hardware to support the entire Nios II instruction set. In such a core, instructions without hardware support are known as unimplemented instructions.The processor generates an exception whenever it issues an