【正文】 evaluated in hardware, at a possible cost in precision.If you do not wish floatingpoint constants tobe cast down to single precision values, append Lto each constant value, to instruct the piler to treat the constant as a doubleprecision floatingpoint value. In this case, if an expression contains a floatingpoint constant, each term in the expression is cast to double precision. As a result, the expression is puted with softwareimplemented doubleprecision arithmetic, at a possible cost in putation speed.With the GCC 4 piler tool chain, prepiled libraries are piled with doubleprecision floatingpoint constants. The behavior of prepiled floatingpoint library functions such as sin()and cos()is unaffected by the presence of the floatingpoint custom instructions. Reset and Debug SignalsFor more information on adding reset signals to the Nios II processor, refer to “Advanced Features Tab” in the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook. For more information on the break vector and adding debug signals to the Nios II processor, refer to “JTAG Debug Module Tab” in the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook.Exception and Interrupt ControllersThe Nios II processor includes hardware for handling exceptions, including hardware interrupts. It also includes an optional external interrupt controller (EIC) interface. The EIC interface enables you to speed up interrupt handling in a plex system by adding a custom interrupt controller.Exception ControllerThe Nios II architecture provides a simple, nonvectored exception controller to handle all exception types. Each exception, including internal hardware interrupts, causes the processor to transfer execution to an exception address. An exception handler at this address determines the cause of the exception and dispatches an appropriate exception routine.Exception addresses are specified with the Nios II Processor parameter editor in Qsys and SOPC Builder.All exceptions are precise. Precise means that the processor has pleted execution of all instructions preceding the faulting instruction and not started execution of instructions following the faulting instruction. Precise exceptions allow the processor to resume program execution once the exception handler clears the exception.EIC InterfaceAn EIC provides high performance hardware interrupts to reduce your program39。 Qsys and SOPC Builder connect interrupts to the EIC.The EIC selects among active interrupts and presents one interrupt to the Nios II processor, with interrupt handler address and register set selection information. The interrupt selection algorithm is specific to the EIC implementation, and is typically based on interrupt priorities. The Nios II processor does not depend on any specific interrupt prioritization scheme in the EIC. For every external interrupt, the EIC presents an interrupt level. The Nios II processor uses the interrupt level in determining when to service the interrupt.Any external interrupt can be configured as an NMI. NMIs are not masked by the , and have no interrupt level.An EIC can be softwareconfigurable.When the EIC interface and shadow register sets are implemented on the Nios II core, you must ensure that your software is built with the Nios II EDS version or higher. Earlier versions have an implementation of the eret instruction that is inpatible with shadow register sets.For a typical example of an EIC, refer to the Vectored Interrupt Controller chapter in the Embedded Peripherals IP User Guide. For details about EIC usage, refer to “Exception Processing” in the Programming Model chapter of the Nios II Processor Reference Handbook. Internal Interrupt ControllerThe Nios II architecture supports 32 internal hardware interrupts. The processor core has 32 levelsensitive interrupt request (IRQ) inputs, irq0through irq31, providing a unique input for each interrupt source. IRQ priority is determined by software. The architecture supports nested interrupts. Your software can enable and disable any interrupt source individually through the ienable control register, which contains an interruptenable bit for each of the IRQ inputs. Software can enable and disable interrupts globally using the PIE bit of the status control register. A hardware interrupt is generated if and only if all of the following conditions are true: ■ The PIE bit of the status register is 1■ An interruptrequest input, irqn, is asserted■ The corresponding bit nof the ienable register is 1In SOPC Builder, the Nios II processor core offers an interrupt vector custom instruction, which accelerates interrupt vector dispatch to reduce your program’s interrupt latency. The interrupt vector custom instruction is less efficient than using the EIC interface with the Altera vectored interrupt controller ponent, and thus is deprecated in Qsys. Altera remends using the EIC interface.For information about adding the interrupt vector custom instruction to the Nios II processor in SOPC Builder, refer to “Custom Instruction Tab” in the Instantiating the Nios II Processor chapter of the Nios II Processor Reference Handbook.Memory and I/O OrganizationThis section explains hardware implementation details of the Nios II memory and I/O organization. The discussion covers both general concepts true of all Nios II processor systems, as well as features that might change from system to system. The flexible nature of the Nios II memory and I/O organization are the most notable difference between Nios II processor systems and traditional microcontrollers. Because Nios II processor systems are configurable, the memories and peripherals vary from system to system. As a result, the memory and I/O organization varies from system to system.A Nios II core uses one or more of the following to provide memory and I/O access:■ Instruction master port—An Avalon174