經(jīng)老師這正后修改文件理解(編輯修改稿)
2025-09-14 16:51 本頁面
【文章內(nèi)容簡介】 DOWNTO 0)。 DATA_N : IN STD_LOGIC_VECTOR(3 DOWNTO 0)。 MIMAIN : OUT STD_LOGIC。 SETIN : OUT STD_LOGIC。 OLD : OUT STD_LOGIC。 ENLOCK : OUT STD_LOGIC。 DATA_BCD : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) )。END COMPONENT。SIGNAL DATA_BCD : STD_LOGIC_VECTOR(15 DOWNTO 0)。SIGNAL SYNTHESIZED_WIRE_0 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_1 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_2 : STD_LOGIC。SIGNAL SYNTHESIZED_WIRE_3 : STD_LOGIC_VECTOR(3 DOWNTO 0)。SIGNAL SYNTHESIZED_WIRE_4 : STD_LOGIC_VECTOR(3 DOWNTO 0)。BEGIN b2v_inst1 : ymPORT MAP(DATA_BCD = DATA_BCD(3 DOWNTO 0), DOUT7 = SEG_SM1)。b2v_inst2 : srPORT MAP(CLK_1K = CLK, KEY_IN = KEY, DATA_M = SYNTHESIZED_WIRE_0, DATA_B = SYNTHESIZED_WIRE_1, CQD = SYNTHESIZED_WIRE_2, CSR = CRS, DATA_F = SYNTHESIZED_WIRE_3, DATA_N = SYNTHESIZED_WIRE_4, KSEL = SEL)。b2v_inst3 : ctrlPORT MAP(DATA_M = SYNTHESIZED_WIRE_0, DATA_B = SYNTHESIZED_WIRE_1, CQD = SYNTHESIZED_WIRE_2, DATA_F = SYNTHESIZED_WIRE_3, DATA_N = SYNTHESIZED_WIRE_4, MIMAIN = MIMAIN, SETIN = SETIN, OLD = OLD, ENLOCK = ENLOCK, DATA_BCD = DATA_BCD)。b2v_inst4 : ymPORT MAP(DATA_BCD = DATA_BCD(15 DOWNTO 12), DOUT7 = SEG_SM4)。b2v_inst5 : ymPORT MAP(DATA_BCD = DATA_BCD(11 DOWNTO 8), DOUT7 = SEG_SM3)。b2v_inst6 : ymPORT MAP(DATA_BCD = DATA_BCD(7 DOWNTO 4), DOUT7 = SEG_SM2)。END bdf_type。 整體原理文件 頂層模塊仿真
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