一個(gè)異步fifo的設(shè)計(jì)示例(編輯修改稿)
2025-07-26 19:15 本頁面
【文章內(nèi)容簡介】 data_in, data_out, r_en, w_en, r_clk, w_clk, full, empty, rst )。 input [7:0]data_in。input r_en。input w_en。input r_clk。input w_clk。input rst。output [7:0]data_out。output empty。output full。wire [7:0]w_addr。wire [7:0]r_addr。wire [7:0]w_addr_nt。wire [7:0]r_addr_nt。ram u1( .data_out(data_out), .data_in(data_in), .w_clk(w_clk), .r_clk(r_clk), .w_en(w_en), .r_en(r_en), .w_addr(w_addr), .r_addr(r_addr) )。w_addr_reg u2( .w_addr(w_addr), .w_addr_nt(w_addr_nt), .w_clk(w_clk), .rst(rst) )。r_addr_reg u3( .r_addr(r_addr), .r_addr_nt(r_addr_nt), .r_clk(r_clk), .rst(rst) )。w_addr_adder u4( .w_en(w_en), .w_addr(w_addr), .w_addr_nt(w_addr_nt) )。r_addr_adder u5( .r_en(r_en), .r_addr(r_addr), .r_addr_nt(r_addr_nt) )。cmp u6( .w_addr(w_addr), .r_addr(r_addr), .full(full), .empty(empty) )。 endmodulemodule ram( data_out, data_in, w_clk, r_clk, w_en, r_en, w_addr, r_addr )。input [7:0]data_in。input w_clk。input r_clk
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鄂ICP備17016276號-1