【文章內(nèi)容簡介】 e tools, hardware description language of the logic description method for the system to plete the design documents, automatically plete logic simplification Logical partitioning, logic synthesis, and logic optimization and simulation and many other functions, until the performance of electronic circuits to achieve the wanted system functions. EDA technology allows designers to just use the software, namely the use of hardware description language (HDL) and EDA software to plete the implementation of the system hardware functions.FPGA (Field Programmable Gate Array) is the mainstream ASIC(Application Specific Integrated Circuits) target device. It is characterized by a direct useroriented, has great flexibility and versatility, ease of use, hardware testing and implementation of fast development of high efficiency, low cost and short time to market, technology and simple maintenance, good reliability and so on.VHDL (Very High Speed Integrated Circuit Hardware Description Language) is initial created by the . Department of Defense. Development so far, it has bee the mainstream of electronic design hardware description languages.This design, which is based on FPGA development platform, the Quartus Ⅱ and Maxplus Ⅱ electronic design software development environment, plete and achieve the design of taxi meter circuit using VHDL text designed method. This report firstly centers on the petition and selection of different solutions。 Secondly, divide the system into different modules, starting from the bottom VHDL’s file, introduce each port connected to each module and functional analysis, and showing the puter simulation results of the analysis。 Thirdly, analyzing the toplevel VHDL’s file, and the final synthesis and simulation results of this system is given, which analyze the top layers file using the topdown design method. The last but not least, it is to analyze the results to hardware verification.7參考文獻[1].潘松,——：1～5.8附錄library ieee。use 。use 。entity distance_counter is port(clk,clr,en,load:in std_logic。記路程的時鐘，清零信號，計數(shù)使能（也即暫停信號），異步置位（也即啟動信號） dout:out std_logic_vector(15 downto 0)。路程的輸出 dout_sm:out std_logic_vector(11 downto 8)。公里數(shù)輸出，作為狀態(tài)機的檢測信號 cout0,cout1:out std_logic)。滿百米的進位（作為計費的時鐘，百米計費一次），滿100Km超量程的進位end distance_counter。architecture bhv of distance_counter isbeginprocess(clk,clr,en,load)variable q:std_logic_vector(15 downto 0)。begin if (clr=39。139。 or load=39。139。) then q:=(others=39。039。)。清零或置位有效 elsif (clk39。event and clk=39。139。) then if en=39。039。 then if q(3 downto 0)1001 then q(3 downto 0):=q(3 downto 0)+1。個位+1 else q(3 downto 0):=0000。 個位有進位 if q(7 downto 4)1001 then q(7 downto 4):=q(7 downto 4)+1。十位+1 else q(7 downto 4):=0000。 if q(11 downto 8)1001 then q(11 downto 8):=q(11 downto 8)+1。百位+1 else q(11 downto 8):=0000。百位有進位 if q(15 downto 12)1001 then q(15 downto 12):=q(15 downto 12)+1。 else q(15 downto 12):=0000。 end if。 end if。 end if。 end if。 end if。 end if。 if q(3 downto 0)=1001 then cout0=39。039。滿百米的進位 else cout0=39。139。 end if。 if q(15 downto 12)=1001 then cout1=39。039。滿100Km的進位 else cout1=39。139。 end if。 dout=q。 dout_sm=q(11 downto 8)。end process。end bhv。library ieee。use 。use 。entity state_machine is port(clk,stop,pause,start:in std_logic。時鐘，清零，暫停，啟動信號 distance:in std_logic_vector(3 downto 0)。 路程公里數(shù)輸入 dataout:out std_logic_vector(1 downto 0)輸出計費控制信號 )。end state_machine。architecture bhv of state_machine istype states is(st0,st1,st2,st3)。定義四個狀態(tài)signal current_state, next_state:states:=st0。beginREG:process(clk,stop)主控時序進程 begin if stop=39。139。 then current_state=st0。 elsif clk39。event and clk=39。139。 then current_state=next_state。 end if。 end process REG。COM:process(current_state,stop,pause,start,distance)主控組合進程 begin case current_state is when st0= dataout=00。路程，車費清零狀態(tài) if pause=39。139。 then next_state=st0。 elsif start=39。139。 then next_state=st1。 elsif stop=39。139。 then next_state=st0。 else next_state=st0。 end if。 when st1= dataout=00。路程小于3公里狀態(tài) if distance0011 then if pause=39。139。 then next_state=st1。 elsif stop=39。139。 then next_state=st0。 else next_state=st1。 end if。 else next_state=st2。 end if。 when st2= dataout=01。路程大于3Km,小于9Km狀態(tài) if distance1001 then if pause=39。139。 then next_state=st2。 elsif stop=39。139。 then next_state=st0。 else next_state=st2。 end if。 else next_state=st3。 end if。 when st3= dataout=10。 大于9Km if pause=39。139。 then next_state=st3。 elsif stop=39。139。 then next_state=st0。 else next_state=st3。 end if。 when others= next_state=st0。 end case。 end process COM。end bhv。library ieee。use 。use 。entity counter_fare is port(clk,clr,en,load:in std_logic。記費用的時鐘（來自路程百米的進位），清零信號，計數(shù)使能（也即暫停信號），異步置位（也即啟動信號） datain:in std_logic_vector(1 downto 0)。來自狀態(tài)機的控制信號，影響計費標準 dout:out std_logic_vector(15 downto 0)。路費的輸出 cout:out std_logic)。滿百元超量程的進位end counter_fare。architecture bhv of counter_fare isconstant add0:std_logic_vector(7 downto 0):=00000000。constant add1:std_logic_vector(7 downto 0):=00100010。constant add2:std_logic_vector(7 downto 0):=00110011。add0,add1,add2是三個計費標準constant load0:std_logic_vector(15 downto 0):=0000000000000000。constant load1:std_logic_vector(15 downto 0):=0000011100000000。load0，load1是兩個