電路參數及其提取ppt課件(編輯修改稿)
2025-05-28 18:20 本頁面
【文章內容簡介】 effort 與電路拓撲結構相關，與器件的尺寸無關 Effective fanout (electrical effort) 是負載和器件尺寸的函數 邏輯門中的延遲 門延遲的仔細區(qū)分 依賴于負載和邏輯特性 依賴寄生特性 22 Department of Microelectronics, PKU， Xiaoyan Liu Logical Effort ? 反相器的 logical effort 和 intrinsic delay 是所有靜態(tài)CMOS 門中最小的，取為 1 ? Logical effort 是該邏輯門和反相器在流過相同電流的條件下邏輯門的輸入電容與反相器的輸入電容的比值，它獨立于 MOSFET的尺寸 ? 邏輯門越復雜， Logical effort 越大 Logical effort 是該邏輯門和反相器在流過相同電流的條件下邏輯門的輸入電容與反相器的輸入電容的比值 g = 1 g = 4/3 g = 5/3 BAA BFVDDVDDA BABFVDDAAF12 2 2221 144Inverter 2input NAND 2input NORA + B A B A B A B A ? B A B A A A 2 1 Cunit = 3 2 2 2 2 Cunit = 4 4 4 1 1 Cunit = 5 24 Department of Microelectronics, PKU， Xiaoyan Liu 各輸入端的 LE可能不一樣 A B C 25 Department of Microelectronics, PKU， Xiaoyan Liu Logical Effort 26 Department of Microelectronics, PKU， Xiaoyan Liu 對于非標準邏輯門 和非標準但 K相同的反相器比 等效反相器為 27 Department of Microelectronics, PKU， Xiaoyan Liu Logical Effort of Gates Fanout (h) Normalized delay (d) t 1 2 3 4 5 6 7 pINV t pNAND F(Fanin) g = 1 p = 1 d = h+1 g = 4/3 p = 2 d = (4/3)h+2 28 Department of Microelectronics, PKU， Xiaoyan Liu d = h + p＝ g f＋ p 對于扇出為 4的標準反相器 g=1, f=4 若 g＝ 0， p＝ 0, d=gf+p=4 若 g ＝ 1， p＝ 1, d=gf+p=5 對于 N級標準反相器構成的環(huán)振 g=1, f=1 若 g ＝ 0， p＝ 0, d1=gf+p=1 D＝ Nd1＝ N， freq＝ 1/2*N 若 g ＝ 1， p＝ 1, d1=gf+p=2 D＝ Nd1＝ 2*N， freq＝ 1/4*N 29 Department of Microelectronics, PKU， Xiaoyan Liu Stage effort: hi = gifi Path electrical effort: F = Cout/Cin Path logical effort: G = g1g2… gN Branching effort: B = b1b2…b N Path effort: H = GFB Path delay D = Sdi = Spi + Shi ? ??????Niiii fgpD e la y1
教學課件相關推薦
鄂ICP備17016276號-1