【文章內(nèi)容簡介】 ccumulator correspond to the points on the cycle of the output sine wave.The phase accumulator is actually a modulo M counter that increments its stored number each time it receives a clock pulse. The magnitude of the increment is determined by the binarycoded input word (M). This word forms the phase step size between referenceclock updates。 it effectively sets how many points to skip around the phase wheel. The larger the jump size, the faster the phase accumulator overflows and pletes its equivalent of a sinewave cycle. The number of discrete phase points contained in the wheel is determined by the resolution of the phase accumulator (n), which determines the tuning resolution of the DDS. For an n = 28bit phase accumulator, an M value of 0000...0001 would result in the phase accumulator overflowing after 28 referenceclock cycles (increments). If the M value is changed to 0111...1111, the phase accumulator will overflow after only 2 referenceclock cycles (the minimum required by Nyquist). This relationship is found in the basic tuning equation for DDS architecture:where: fOUT = output frequency of the DDS M = binary tuning word fC = internal reference clock frequency (system clock) n = length of the phase accumulator, in bits Changes to the value of M result in immediate and phasecontinuous changes in the output frequency. No loop settling time is incurred as in the case of a phaselocked loop. As the output frequency is increased, the number of samples per cycle decreases. Since sampling theory dictates that at least two samples per cycle are required to reconstruct the output waveform, the maximum fundamental output frequency of a DDS is fC/2. However, for practical applications, the output frequency is limited to somewhat less than that, improving the quality of the reconstructed waveform and permitting filtering on the output. When generating a constant frequency, the output of the phase accumulator increases linearly, so the analog waveform it generates is inherently a ramp. Then how is that linear output translated into a sine wave? Figure 5. Signal flow through the DDS architecture.A phase to amplitude lookup table is used to convert the phaseaccumulator’s instantaneous output value (28 bits for AD9833)—with unneeded lesssignificant bits eliminated by truncation—into the sinewave amplitude information that is presented to the (10 bit) D/A converter. The DDS architecture exploits the symmetrical nature of a sine wave and utilizes mapping logic to synthesize a plete sine wave from onequartercycle of data from the phase accumulator. The phaseto amplitude lookup table generates the remaining data by reading forward then back through the lookup table. This is shown pictorially in Figure 5.What are popular uses for DDS? Applications currently using DDSbased waveform generation fall into two principal categories: Designers of munications systems requiring agile (., immediately responding) frequency sources with excellent phase noise and low spurious performance often choose DDS for its bination of spectral performance and frequencytuning resolution. Such applications include using a DDS for modulation, as a reference for a PLL to enhance overall frequency tunability, as a local oscillator (LO), or even for direct RF transmission. Alternatively, many industrial and biomedical applications use a DDS as a programmable waveform generator. Because a DDS is digitally programmable, the phase and frequency of a waveform can be easily adjusted without the need to change the external ponents that would normally need to be changed when using traditional analogprogrammed waveform generators. DDS permits simple adjustments of frequency in real time to locate resonant frequencies or pensate for temperature drift. Suchapplications include using a DDS in adjustable frequency sources to measure impedance (for example in an impedancebased sensor), to generate pulsewave modulated signals for microactuation, or to examine attenuation in LANs or telephone cables. What do you consider to be the key advantages of DDS to designers of realworld equipment and systems? Today’s cost petitive, high performance, functionally integrated DDS ICs are being mon in both munication systems and sensor applications. The advantages that make them attractive to design engineers include: ? digitally controlled microhertz frequencytuning and subdegree phasetuning capability, ? extremely fast hopping speed in tuning output frequency (or phase)。 phase continuous frequency hops with no overshoot/undershoot or analogrelated loop settlingtime anomalies, ? the digital architecture of DDS eliminates the need for the manual tuning and tweaking related to ponent aging and temperature drift in analog synthesizer solutions, and ? the digital control interface of the DDS architecture facilitates an environment where systems can be remotely controlled and optimized with high resolution under processor control. How would I use a DDS device for FSK encoding? Figure 6. FSK modulation.Binary frequencyshift keying (usually referred to simply as FSK) is one of the simplest forms of data encoding. The data is transmitted by shifting the frequency of a continuous carrier to one of two discrete frequencies (hence binary). One frequency, f1, (perhaps the higher) is designated as the mark frequency (binary one) and the other, f0, as the space frequency (binary zero). Figure 6 shows an example of the relationship between the markspace data and the transmitted signal.Figure 7. A DDSbased FSK encoder.This encoding scheme is easily implemented using a DDS. The DDS frequency tuning word, representing the output frequencies, is set to the appropriate values to generate f0 and f1 as they occur in the pattern of 0s and 1s to be transmitted. The user programs the two required tuning words into the device before transmission. In the case of the AD9834, two freq