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cation, and shorter timetomarket. As design trends continue to move to higher levels of abstraction, more emphasis will continue to be placed in verification activities at both the ponent and system level. The creation of a “virtual” system using accurate models of the hardware provides engineers with the following benefits: an architectural exploration of hardware and software functions, the creation of flexible prototype hardware, more accurate analysis of throughput and portability, software development earlier in the cycle, and rapid debugging through the instrumentation of the virtual hardware. One of the primary advantages of a virtual system implementation is architecture exploration, which is the process of determining an optimum solution to a design space problem. Take for example the twodimensional architectural space shown in Figure 1. The two design parameters shown (typically there are many design parameters) are power consumption and clock speed, with the ideal solution illustrated by the center of the target. In this simplified example, the yellow cross illustrates a hardware prototype ECU that exceeds the ideals for power consumption and fails to meet the clock speed ideals. Because of the timetomarket constraint, the system architecture continues to be based upon the initial hardware prototype without adequate exploration of alternative choices. The end result of a hardware based development process is a suboptimum product that may miss the design targets. Conversely the green crosses show an alternative path to the optimum design solution. Several virtual systems are assembled and tested in the same timetomarket window. The final virtual system is ontarget for the design parameters, and the resulting work products from the virtual system are quickly converted into the physical product. Models of the system are initially created at a high level of abstraction, and, through the modelbased methodology, are driven to a full virtual implementation, then to an actual product. The modelbased methodology approach proposes the use of an architecture exploration tool to facilitate the rapid exploration of various CPUs, memories, and peripherals (system architecture). The system architecture is shown in the upper right of Figure 2 . The upper left of Figure 2 shows early revisions of the functional models of the system, known as system behavior. The system behavior and system architecture are bined, and an optimal solution is achieved by iteratively paring the performance of each partitioned alternative. The objective is to evaluate the various architectural and partitioning alternatives to gain a first order approximation of the optimum design. Some of the proposed EDA tools for architecture exploration offer the ability to model microcontroller architectures in only a few weeks duration. The simulations for architectural simulation may be only 80% accurate, but that is believed to be good enough to make the first order choices of microcontroller, timer architecture and memory usages. Our evaluations of the architectural exploration tools, h