【正文】 ? 8 bits are encoded into 10 bits 54 12/4/2020 Differential Signaling 下載 8b/10b: Overview ? The 10 bits are referred to as a “symbol” or a “codegroup:” ? The original 8 bits are broken into a 3 bit block and a 5 bit block (each of these are called subblocks) F1 ? 111 10001 ? The 3 bit subblock (labeled HGF) is encoded into 4 new bits (labeled fghj) amp。 Encoding Example: ? Transmitter keeps running track of current disparity (it is either RD, RD+ or neutral) Neutral means the disparity tracker keeps the previous RD or RD+ value ? A Running Disparity of RD+ is always followed by an RD encoding and vice versa If Running Disparity is RD+, the following is encoded for the data byte F1: HGF EDCBA ? abcdei fghj 111 10001 ? 100011 0111 (RD encoding) If Running Disparity is RD, the following is encoded for the data byte F1: HGF EDCBA ? abcdei fghj 111 10001 ? 100011 0001 (RD+ encoding) 63 12/4/2020 Differential Signaling 下載 8b/10b Disparity amp。 (RD+) (although is reserved....) 001111 1000 001111 1000 001100 1100 001111 1000 001100 1100 (RD) (RD+) (RD) (RD+) (RD) amp。 note that the relative order and position of the subblocks is switched upon encoding HGF EDCBA ? abcdei fghj Hence, an extra bit, j , is added to the newly encoded 3 bit block and an extra bit, i , to the encoded 4 bit block creating a 4 and 5 bit subblocks 55 12/4/2020 Differential Signaling 下載 8b/10b – Character Conventions ? Both Data Characters and Special Control Characters exist。 simulation ? Timing parameters Clock recovery Embedded clock ? AC coupling Common mode response Issues with simulation ? 8B10B encoding DC balanced codes ? Duty Cycle distortion Cycle 3 12/4/2020 Differential Signaling 下載 Single Ended Signaling ? All electrical signal circuits require a loop or return path. ? Single ended signal subject several means of distortions and noise. Ground or reference may move due to switching currents (SSO noise). We touched on this in the ground conundrum class. A single ended receiver only cares about a voltage that is referenced to its own ground. Electromagic interference can impose voltage on a single ended signal. Signal passing from one board to another are subject to the local ground disturbance. ? We can counteract many of these effect by adding more ground. ? As frequencies increase beyond 1GHz, 80% of the signal will be lost. 4 12/4/2020 Differential Signaling 下載 Review of threshold sensitivity ? The wave is referenced to either Vcc or Vss. Consequently the effective DC value of the wave will be tied to one of these rails. ? The wave is attenuated around the effective DC ponent of the waveform, but the reference does not change accordingly. Hence the clock trigger point between various clock load points is very sensitive to distortion and attenuation. Tx Vss Vref Vss Rx2 Vref Long line Vss Rx1 Vref Short line 5 12/4/2020 Differential Signaling 下載 Differential Signaling ? Any signal can be considered a loop is pleted by two wires. ? One of the “wires” in single ended signaling is the “ground plane” ? Differential signaling uses two conductors The transmitter translates the single input signal into a pair of outputs that are driven 180176。 Disparity ? Never more than 5 consecutive 1’s or 0’s allowed in a row (consecutively)... the maximum “run rate” is 5 to maintain a DC balanced transmission. ? This guarantees the lowest frequency to be 1/10 of the max frequency. . only 1 decade data bandwidth required. ? With 8b/10b, either positive (RD+) or negative (RD) disparity encoding is possible 57 12/4/2020 Differential Signaling 下載 8b/10b Disparity ? Disparity is “the difference between the number of ones and zeros...positive and negative disparity refer to an excess of ones or zeros respectively”. ? Note: neutral disparity is said to occur when RD+ and RD encoding are identical meaning they will each have the same number of ones and zeros (there are some exceptions) ? A given subblock or symbol can have an actual disparity number of either a zero (neutral), +2 or –2, though the Running Disparity is said only to be Positive, Negative or Neutral. 58 12/4/2020 Differential Signaling 下載 8b/10b – Running Disparity ? The Running or Current Disparity (a binary value of + or ) is tracked by the TX/RX and is puted at every subblock boundary and at each symbol boundary. ? The value from one subblock or symbol is used with that of the next subblock or symbol to give a “running” or “current” status. 59 12/4/2020 Differential Signaling 下載 8b/10b – Running Disparity Algorithm ? For a given encoding of a byte, the starting disparity is what existed at the end of the previous symbol ? The running disparity is then calculated first for the 6 bit subblock, prehending the starting disparity value。 Widmer (IBM) Patent 4,486,739 December 4, 1984, Byte Oriented DC Balanced 8B/10B Partitioned Block Transmission Code ? 3GIO Architecture Specification Key Developer Draft August 21, 2020, Appendix C, pg148154 ? ANSI , clause 11 (and also IEEE , ). 68 12/4/2020 Differential Signaling 下載 Other sources of mon mode ? A DC voltage will build up across the blocking capacitor if the charge and discharge is not equal. ? We have see this can happen if the number of bits is unbalance. ? Another source of imbalance is possible if the duty cycle of the one and zeros is not 50%. ? This can happen in two ways The time for a one differs from that of a zero. This can be caused by edge jitter. The rising time and falling time are miss matched On the next slide we will t