【正文】 diationhardened devices have lot and/or wafer radiation qualification tests performed。s fault tolerant input property when redundant input data is provided to separate storage nodes. The idea is that the redundant input data is provided through a total duplication of binational logic (referred to as “dual rail design”) such that a simple SET on one rail cannot produce an upset. Therefore, some other upset mechanism must be happening. It is possible that a single particle strike is placing an SET on both halves of the logic streams, allowing an SET to produce an upset. Care was taken to separate the dual sensitive nodes in the SERT cell layouts but the automated placeandroute of the binatorial logic paths may have placed dual sensitive nodes close enough. At this point, the theory for the CULPRiT SEU response is that at about an LET of 20, the energy deposition is sufficiently wide enough (and in the right locations) to produce an SET in both halves of the binatorial logic streams. Increasing LET allows for more regions to be sensitive to this effect, yielding a larger cross section. Further, the second SEU mechanism that starts at an LET of about 4060 has to do with when the charge collection disturbance cloud gets large enough to effectively upset multiples of the redundant storage nodes within the SERT cell itself. In this μm library, the node separation is several microns. However, since it takes less charge to upset a node operating at Volts, with transistors having effective thresholds around 70 mV, this is likely the effect being observed. Also the fact that the perbit memory upset cross section for the CULPRiT devices and the mercial technologies are approximately equal, as shown in Figure 9, indicates that the cell itself has bee sensitive to upset. IX. SUMMARY A detailed parison of the SEE sensitivity of a HBD technology (CULPRiT) utilizing the 8051 microcontroller as a test vehicle has been pleted. This paper discusses the test methodology used and presents a parison of the mercial versus CULPRiT technologies based on the data taken. The CULPRiT devices consistently show significantly higher threshold LETs and an immunity to latchup. In all but the memory test at the highest LETs, the cross section curves for all upset events is one to two orders of magnitude lower than the mercial devices. Additionally, theory is presented, based on the CULPRiT technology, that explain these results. This paper also demonstrates the test methodology for quantifying the level of hardness designed into a HBD technology. By using the HBD technology in a realworld device structure (., not just a test chip), and paring results to equivalent mercial devices, one can have confidence in the level of hardness that would be available from that HBD technology in any circuit application. ACKNOWLEDGEMENTS The authors of this paper would like to acknowledge the sponsors of this work. These are the NASA Electronic Parts and Packaging Program (NEPP), NASA Flight Programs, and the Defense Threat Reduction Agency (DTRA). 使用 8051單片機(jī)驗(yàn)證和測(cè)試單粒子效應(yīng)的加固工藝 摘要 隨著 代工業(yè)務(wù) （ 抗輻射加固設(shè)計(jì)的 芯片制造加工廠 專門 從事 的 一項(xiàng)業(yè)務(wù)） 的減少，使用非專用代工業(yè)務(wù) 的 新技術(shù)逐步發(fā)展起來(lái)。本文所介紹的方法是使用加固微創(chuàng)設(shè)計(jì)技術(shù)的工業(yè)代工。這是否需要完成輻射條件測(cè)試？回答這個(gè)問(wèn)題之前，先看一下其他的問(wèn)題。美國(guó)航天局的電子零件封裝（ NEPP ）計(jì)劃是為了探討這些因素的類型。醫(yī)學(xué)研究理事會(huì)和 高級(jí)微電子研究所 都選擇這個(gè)設(shè)備，但他們論證的是兩種截然不同固化工藝。完備進(jìn)程中目的是優(yōu)化 測(cè)試過(guò)程以盡可能獲得完整的評(píng)價(jià)。C ，時(shí)鐘頻率為 24兆赫。 CMOS設(shè)備是 MSC 51系列的一個(gè)版本，與超低功耗（ ULP）進(jìn)程代工許可的 C8051 HDL核心兼容。各主板的所有其他組件需要被測(cè)設(shè)備計(jì)算機(jī)完成，包括在一些設(shè)計(jì)名義上是沒(méi)有必要的組件（如外部?jī)?nèi)存，外部 ROM和地址鎖存器） 。這將確保在測(cè)試時(shí)只有 8051被測(cè)設(shè)備所需的部分在運(yùn)行，并有助于測(cè)試時(shí)發(fā)生錯(cuò)誤的精確定位。 ? “混亂”的例行程序，如果它偏離代碼空間就會(huì)重置 程序計(jì)數(shù)器。當(dāng) 出錯(cuò)信息和寄存器值被傳送， 不斷進(jìn)行比較 ，糾正。 不匹配與已知值和錯(cuò)誤信息被重新裝入。蘇醒后，從重置，通過(guò)執(zhí)行地址 0x0000指令代碼再次啟動(dòng)被測(cè)設(shè)備電腦 ，但這個(gè)時(shí)候，代碼不是啟動(dòng) /串行裝入程序代碼，而是測(cè)試代碼。 八 討論 為什么 CMOS超低功耗輻射容錯(cuò) 設(shè)備不發(fā)生閉鎖現(xiàn)象，主要原因是 作電壓低于閉鎖發(fā)生需要的額定電壓。假設(shè)了單粒子防護(hù)技術(shù)單元拓?fù)浜蛦瘟Ｗ臃D(zhuǎn)節(jié)點(diǎn)，預(yù)計(jì)在單粒子防護(hù)技術(shù)單元將完全不受存在內(nèi)部的存儲(chǔ)單元本身的 SEUs的影響。思路是多余的輸入數(shù)據(jù)是由一個(gè)總的重復(fù)組合邏輯（稱為“雙軌設(shè)計(jì)” ）提供， 這樣一個(gè)防護(hù)上簡(jiǎn)單的 SET就不能產(chǎn)生翻轉(zhuǎn)。 然而，因?yàn)樗恍柝?fù)責(zé)打破 1節(jié)點(diǎn)操作系統(tǒng)在 ，具有與晶體管有效的閾值約 70毫伏，這是可能的效果得到遵守。通過(guò)在器件結(jié)構(gòu)（即，不只是一個(gè)測(cè)試芯片）應(yīng)用 HBD技術(shù) ，以及等價(jià)商業(yè)設(shè)備比較結(jié)果， 人們可以有信心在這一的硬度水平將可從該技術(shù)在任何硬件設(shè)計(jì)電路應(yīng)用。此 外，提出了解釋了這些結(jié)果的理論，這個(gè)理論以 CMOS超低功耗輻射容錯(cuò) 技術(shù)為基礎(chǔ)。 此外，第二個(gè) SEU機(jī)制，開始約 4060線性能量轉(zhuǎn)移，收集足夠多的干擾，能夠有效地翻轉(zhuǎn)的 單粒子防護(hù)技術(shù)元件的 冗余存儲(chǔ)節(jié)點(diǎn)倍數(shù)。 線性能量轉(zhuǎn)移 ， SET（頻變）的組件是位于的“直流偏置” 組件的上面 大概是發(fā)生內(nèi)部的第二次翻轉(zhuǎn)機(jī)制的單粒子防護(hù)技術(shù)元件有效的線性能量轉(zhuǎn)移閘值排在第二位。但是，考慮到實(shí)用的回偏電壓，電壓可以超過(guò)現(xiàn)在的額定電壓。這種定期的數(shù)據(jù)被稱為“遙測(cè)” 。被測(cè)設(shè)備計(jì)算機(jī)下載測(cè)試代碼并把它放入程序代碼存儲(chǔ)器（位于被測(cè)設(shè)備計(jì)算機(jī)主板） 。所有不匹配被更正，錯(cuò)誤信息傳送。計(jì)算和期望值的所有不匹配與其他有關(guān)寄存器信息一起傳送。 ? 外部實(shí)時(shí)時(shí)鐘，作為數(shù)據(jù)錯(cuò)誤標(biāo)記。它的目的是要作為一個(gè)模 塊化設(shè)計(jì)，為被測(cè)設(shè)備的每一個(gè)具體部分的設(shè)計(jì)一系列小型試驗(yàn)程序 。一個(gè)獨(dú)特的硬連線標(biāo)識(shí)符字節(jié)所帶有的小卡（每種被測(cè)設(shè)備封裝類型有一個(gè)）控制被測(cè)設(shè)備，晶體，并旁路電容器（和電壓電平轉(zhuǎn)換為被測(cè)設(shè)備 ） 。此外，重新設(shè)計(jì)技術(shù)核心，最終使該機(jī)器周期縮短，從而得到有效的處理能力，這大約是 （快）比標(biāo)準(zhǔn)的 8052器件。 英特爾的設(shè)備是無(wú)存儲(chǔ)器型，這是經(jīng)典的 8052 MCS 51單片機(jī)電路版。商業(yè)研究一 一比較了他們的成本效益，性能和可靠性。 8051單片機(jī)是一個(gè)行業(yè)標(biāo)準(zhǔn)架構(gòu)，被廣泛接受和應(yīng)用，并作為一種開發(fā)工具。 需要考慮的因素是，設(shè)計(jì)程序庫(kù)，測(cè)試范圍，鑄造特點(diǎn)必須是已知的，并且深刻理解測(cè)試用途 。也就是說(shuō)， 有了測(cè)試芯片，我們是不是就可以在未來(lái)器件上使用相同的程序庫(kù)了？ 試想，如果賣主 A的設(shè)計(jì)的新的固化工藝程序庫(kù)可移植性可比賣主 B和 C的都好，那么 A設(shè)計(jì)，測(cè)試的測(cè)試芯片就是可接受的了。 一 導(dǎo)言 美國(guó)航天局要在空間輻射環(huán)境中最低限度地使用資源條件下，不斷努力提供最好科學(xué)方法 [ 1,2 ] 。s memory space). Upon awaking from the reset, the DUT puter again booted by executing the instruction code at address 0x0000, except this time that code was not be the Boot/Serial Loader code but the Test Code. The Test Control Computer always retained the ability to force the reset/remap function, regardless of the DUT Computer39。 what types of tests are required for HBD validation? II. TESTING HBD DEVICES CONSIDERATIONS Test methodologies in the United States exist to qualify individual devices through standards and anizations such as ASTM, JEDEC, and MILSTD 883. Typically, TID (Co60) and SEE (heavy ion and/or proton) are required for device validation. So what is unique to HBD devices? As opposed to a “regul