【正文】 理工大學(xué)學(xué)士學(xué)位論文 I 摘 要 隨著計(jì)算機(jī)在人們生活中重要性和不可或缺性的提高，為了更方便的為大眾使用，發(fā)展計(jì)算機(jī)性能成為 IT 行業(yè)的熱點(diǎn)，但計(jì)算機(jī)的內(nèi)部結(jié)構(gòu)極其復(fù)雜，為了便于研究便產(chǎn)生了模型計(jì)算機(jī)。 本文完成了基于 VHDL 的 8 位模型計(jì)算機(jī)的設(shè)計(jì)與實(shí)現(xiàn)。文中首先闡述了 8 位模型計(jì)算機(jī)的原理，然后對其十個功能模塊（算術(shù)邏輯運(yùn)算單元，累加器，控制器，地址寄存器，程序計(jì)數(shù)器，數(shù)據(jù)寄存器，存儲器，節(jié)拍發(fā)生器，時鐘信號源，指令寄存器和指令譯碼器）進(jìn)行了分析與設(shè)計(jì)。最后在 Quartus II 環(huán)境下進(jìn)行了仿真，完成了 8 位模型計(jì)算機(jī)的整 體實(shí)現(xiàn)。 本文綜合了計(jì)算機(jī)組成原理和數(shù)字邏輯與系統(tǒng)設(shè)計(jì)的知識， 設(shè)計(jì)的 8 位模型計(jì)算機(jī)能更方便的了解計(jì)算機(jī)內(nèi)部構(gòu)造和工作原理。整個系統(tǒng)的開發(fā)體現(xiàn)了在 Quartus II 軟件平臺上用 VHDL 設(shè)計(jì)數(shù)字控制系統(tǒng)的實(shí)用性。 關(guān)鍵詞 ： 8 位模型機(jī) ； Quartus II ； VHDL 語言 理工大學(xué)學(xué)士學(xué)位論文 II Abstract With the improvement of importance and indispensability in puter in people39。s life,in order to use more conveniently for public ,puter performance is being a hot in the IT industry the internal structure of the puter is very plicate,Computer model simplifies the difficulty of the research. This article pleted the design and implementation of eight model puter based on ,this article expounds the principle of eight model puter,then divides it into 10 modules(arithmetic logic unit, accumulator, controllers, address register, the program counter and data registers, memory, beat generator, a clock signal, instruction register and instruction decoder)and analyse and design each of under the environment of the Quartus II simulation, pleted overall implementation of the 8 model puter. The analysis and design of the eight model puter integrated the knowledge of puter constitute principle and Digital logic and system design. The design of the eight model puter can be more convenient to understand internal structure and working whole system development manifests the practicability of designing the numerical control system on the Quartus II software platform with VHDL. Key words: eight model puter 。 VHDL language。 Quartus II 理工大學(xué)學(xué)士學(xué)位論文 III 目 錄 1 緒論 ...................................................................................................................................... 1 本課題研究的目的 .................................................................................................... 1 本課題研究的背景及意義 ........................................................................................ 1 2 基于 VHDL 編程的基礎(chǔ)知識 ............................................................................................. 4 VHDL 語言概述 ........................................................................................................ 4 VHDL 的設(shè)計(jì)流程 .................................................................................................... 5 有關(guān) Quartus II 的介紹 ............................................................................................. 6 本課題基于 Quartus II 的設(shè) 計(jì)流程 .......................................................................... 8 3 基于 VHDL8 位模型機(jī)的原理與設(shè)計(jì) ............................................................................... 9 模型計(jì)算機(jī)的原理 .................................................................................................... 9 模型機(jī)的總體設(shè)計(jì)要求 ............................................................................................ 9 模型機(jī)邏輯框圖的設(shè)計(jì) .......................................................................................... 10 模型機(jī)的指令系統(tǒng)設(shè)計(jì) .......................................................................................... 10 模型機(jī)的指令執(zhí)行流程設(shè)計(jì) .................................................................................. 11 基于 VHDL8 位模型機(jī)各模塊的設(shè)計(jì)與實(shí)現(xiàn) ....................................................... 12 算術(shù)邏輯單元 ALU 模塊 .............................................................................. 12 累加器模塊 .................................................................................................... 14 控制器模塊 .................................................................................................... 18 節(jié)拍發(fā)生器 .................................................................................................... 21 指令寄存器模塊 IR 和指令譯碼器 .............................................................. 24 時鐘產(chǎn)生器 .................................................................................................... 28 程序計(jì)數(shù)器模塊 ............................................................................................ 30 地址寄存器 MAR .......................................................................................... 33 存儲器 RAM .................................................................................................. 36 數(shù)據(jù)寄存器 DR ............................................................................................ 38 4 基于 VHDL 的 8 位模型計(jì)算機(jī)的實(shí)現(xiàn) ........................................................................... 42 基于 VHDL 的微程序執(zhí)行流程圖 ......................................................................... 42 8 位模型機(jī)的頂層原理圖設(shè)計(jì) ............................................................................... 43 理工大學(xué)學(xué)士學(xué)位論文 IV 基于 VHDL 的 8 位模型機(jī)工作流程 ..................................................................... 44 頂層 VHDL 源程序設(shè)計(jì) ......................................................................................... 45 頭文件 cpu_defs 的 VHDL 設(shè)計(jì) ................................................................... 45 CPU 的 VHDL 源程序設(shè)計(jì) .......................................................................... 46 8 位模型機(jī)的整體實(shí)現(xiàn) ........................................................................................... 54 結(jié) 論 ........................................................................................................................................ 57 致 謝 ........................................................................................................................................ 58 參考文獻(xiàn) .................................................................................................................................. 59 附錄 A 英文原文 .............