外文翻譯---三星s3c2442b32位精簡(jiǎn)指令應(yīng)用處理器用戶(hù)手冊(cè)(已修改)
2025-06-01 11:03 本頁(yè)面
【正文】 天津工程師范學(xué)院 2020 屆本科生畢業(yè)設(shè)計(jì) 1 英文資料 S3C2442B 32BIT RISC APPLICATION PROCESSOR USER’S MANUAL INTRODUCTION This user’s manual describes SAMSUNG39。s SC32442B 16/32bit RISC microprocessor. SAMSUNG’s SC32442B is designed to provide handheld devices and general applications with lowpower, and highperformance microcontroller solution in small die size. To reduce total system cost, the SC32442B includes the following ponents. The SC32442B is developed with ARM920T core, CMOS standard cells and a memory plier. Its lowpower, simple, elegant and fully static design is particularly suitable for cost and powersensitive applications. It adopts a new bus architecture known as Advanced Micro controller Bus Architecture (AMBA). The SC32442B offers outstanding features with its CPU core, a 16/32bit ARM920T RISC processor designed by Advanced RISC Machines, Ltd. The ARM920T implements MMU, AMBA BUS, and Harvard cache architecture with separate 16KB instruction and 16KB data caches, each with an 8word line length. By providing a plete set of mon system peripherals, the SC32442B minimizes overall system costs and eliminates the need to configure additional ponents. The integrated onchip functions that are described in this document include: ◆ Around arm and internal, arm and internal, , external I/O microprocessor with 16KB ICache/16KB DCache/MMU ◆ External memory controller (SDRAM Control and Chip Select logic) ◆ LCD controller (up to 4K color STN and 256K color TFT) with LCDdedicated DMA ◆ 4ch DMA controllers with external request pins ◆ 3ch UARTs (, 64Byte Tx FIFO, and 64Byte Rx FIFO) ◆ 2ch SPls ◆ IIC bus interface (multimaster support) ◆ IIS Audio CODEC interface ◆ SD Host interface version amp。 MMC Protocol version patible ◆ 2ch USB Host controller / 1ch USB Device controller (ver ) ◆ 4ch PWM timers / 1ch Internal timer / Watch Dog Timer ◆ 8ch 10bit ADC and Touch screen interface ◆ RTC with calendar function ◆ Camera interface (Max. 4096 x 4096 pixels input support. 2048 x 2048 pixel input support for scaling) ◆ 130 General Purpose I/O ports / 24ch external interrupt source 天津工程師范學(xué)院 2020 屆本科生畢業(yè)設(shè)計(jì) 2 ◆ Power control: Normal, Slow, Idle, stop and Sleep mode ◆ Onchip clock generator with PLL FEATURES ◆ Architecture ? Integrated system for handheld devices and general embedded applications. ? 16/32Bit RISC architecture and powerful instruction set with ARM920T CPU core. ? Enhanced ARM architecture MMU to support WinCE, EPOC 32 and Linux. ? Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance. ? ARM920T CPU core supports the ARM debug architecture. ? Internal Advanced Microcontroller Bus Architecture (AMBA) (, AHB/APB). ◆ System Manager ? Little/Big Endian support. ? Support Fast bus mode and Asynchronous bus mode. ? Address space: 128M bytes for each bank (total 1G b
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