外文翻譯---三星s3c2442b32位精簡指令應用處理器用戶手冊-文庫吧
2025-04-17 11:03 本頁面
【正文】 ytes). ? Supports programmable 8/16/32bit data bus width for each bank. ? Fixed bank start address from bank 0 to bank 6. ? Programmable bank start address and bank size for bank 7. ? Eight memory banks:– Six memory banks for ROM, SRAM, – Two memory banks for ROM/SRAM/ Synchronous DRAM. ? Complete Programmable access cycles for all memory banks. ? Supports external wait signals to expand the bus cycle. ? Supports selfrefresh mode in SDRAM for powerdown. ? Supports various types of ROM for booting (NOR/NAND Flash, EEPROM, and others). ◆ NAND Flash Boot Loader ? Supports booting from NAND flash memory. ? 4KB internal buffer for booting. ? Supports storage memory for NAND flash memory after booting. ? Supports Advanced NAND flash ◆ Cache Memory ? 64way setassociative cache with ICache (16KB) and DCache (16KB). ? 8words length per line with one valid bit and two dirty bits per line. ? Pseudo random or round robin replacement algorithm. ? Writethrough or writeback cache operation to update the main memory. ? The write buffer can hold 16 words of data and four addresses. ◆ Clock amp。 Power Manager ? Onchip MPLL and UPLL: UPLL generates the clock to operate USB Host/Device. MPLL generates the clock to operate MCU at maximum arm and internal, 天津工程師范學院 2020 屆本科生畢業(yè)設計 3 arm and internal,. ? Clock can be fed selectively to each function block by software. — Power mode: Normal, Slow, Idle, Deepstop and Sleep mode — Normal mode: Normal operating mode — Slow mode: Low frequency clock without PLL — Idle mode: The clock for only CPU is stopped. — Stop mode: All clocks are stopped. — DeepStop mode: Arm power off internal clocks are stopped. — Sleep mode: The Core power including all peripherals is shut down. ? Woken up by EINT[15:0] or RTC alarm interrupt from Sleep mode ◆ Stacked Memory ? 256Mbit or 512Mbit mSDR x32, VDD= ? 512Mbit or 1Gbit Nand Flash x8, VDD= ◆ Interrupt controller ? 59 Interrupt sources (One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1 SDI, 2 USB, 1 LCD, 1 Battery Fault, 1 NAND and 2 Camera) ? Level/Edge mode on external interrupt source ? Programmable polarity of edge and level ? Supports Fast Interrupt request (FIQ) for very urgent interrupt request ◆ Timer with Pulse Width Modulation (PWM) ? 4ch 16bit Timer with PWM / 1ch 16bit internal timer with DMAbased or interruptbased operation ? Programmable duty cycle, frequency, and polarity ? Deadzone generation ? Supports external clock sources ◆ RTC (Real Time Clock) ? Full clock feature: msec, second, minute, hour, date, day, month, and year ? KHz operation ? Alarm interrupt ? Time tick interrupt ? RTC Low Battery Check ◆ General Purpose Input/Output Ports ? 24 external interrupt ports ? 130 Multiplexed input/output ports ◆ DMA Controller ? 4ch DMA controller ? Supports memory to memory, IO to memory, memory to IO, and I
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鄂ICP備17016276號-1